Method for configuring chip selects in memories
View Patent ↗Embodiments of the present invention relate to an electronic device having programmable chip enable inputs in that each chip enable has a programmable assertion level, e.g., high or low. The device may be an integrated memory chip, e.g., SRAM device. On power up, a JTAG input port of the electronic device can be used to program a configuration register which contains bits for setting the assertion level of each chip enable input. The bits may be used to control respective multiplexers which select between a chip enable signal and its inverse. The chip enable signals may originate from a controller device. Regarding a memory device, the outputs of the multiplexers are coupled to chip enable signals of an integrated memory core. The pre-configurable chip selects comprise chip select pins which are individually configured to active-high or active-low configurations so that the number of selectable memory chips requires only a number of chip selects equal to the number of times a memory is doubled, plus one chip select.
1. A method for addressing computer memory, comprising: configuring a set of chip select levels for a memory chip and forming configuration data representing said chip select levels; storing said configuration data in a programmable data register in said memory chip; receiving chip select signals at said memory chip; and enabling said memory chip in accordance with said configuration data and said chip select signals.
2. The method as described in claim 1 , wherein said configuring comprises configuring said chip select levels to a chip-specific configuration with respect to a plurality of memory chips.
3. The method as described in claim 2 , wherein said chip select levels are configured to states selected from active-high and active-low states.
4. The method as described in claim 3 , wherein said chip select levels are configured differently between memory chips of a same memory bank.
5. The method as described in claim 3 , wherein said chip select levels are controlled by said configuration data in said programmable data register.
6. The method as described in claim 1 , wherein said programmable data register resides in a JTAG compliant circuit.
7. The method as described in claim 6 , wherein said programmable data register is user defined.
8. An integrated computer memory chip, comprising: a memory core; a circuit for controlling chip select levels of said memory chip and for receiving chip select signals; and a programmable data register for storing configuration data for configuring said circuit, wherein said chip select levels are adapted to be configured individually for said memory chip among a plurality of memory chips of a bank of memory.
9. The computer memory chip as described in claim 8 , wherein said computer memory chip is an SRAM device.
10. The computer memory chip as described in claim 8 , wherein said chip select levels are configured in said programmable data register.
11. The computer memory chip as described in claim 8 , wherein said chip select levels are configured by said configuration data.
12. The computer memory chip as described in claim 8 wherein said circuit for controlling chip select levels comprises a plurality of multiplexers, each multiplexer receiving a chip select signal and an inverted chip select signal and each multiplexer controlled by a respective bit of said programmable data register.
13. The computer memory chip as described in claim 12 wherein outputs of said plurality of multiplexers are coupled to chip enables of said memory core for enabling thereof.
14. The computer memory chip as described in claim 12 wherein said circuit for controlling chip select levels further comprises a plurality of inverter gates for generating the inverted chip selects.
15. An electronic system comprising: a controller for generating a plurality of chip select signals; and a plurality of integrated circuit devices coupled to, and addressed by, said plurality of chip select signals, wherein each integrated circuit device comprises: a plurality of programmable chip enable inputs, wherein each chip enable input has a programmable assertion level which is maintained internally by each integrated circuit device.
16. An electronic system as described in claim 15 wherein said plurality of integrated circuit devices are memory chips.
17. An electronic system as described in claim 15 wherein each integrated circuit device further comprises a programmable configuration register for storing data representing programmable assertion levels of said plurality of programmable chip enable inputs.
18. An electronic system as described in claim 17 wherein each integrated circuit device further comprises logic for implementing said programmable assertion levels of said plurality of programmable chip enable inputs, said logic coupled to said programmable configuration register.
19. An electronic system as described in claim 18 wherein said logic comprises a plurality of multiplexers, each multiplexer corresponding to a respective programmable chip enable input.
20. An electronic system as described in claim 15 wherein said plurality of programmable chip enable inputs are programmable via a JTAG input port of each integrated circuit device.