IP Library Granted Patent US 8,481,366
Granted Patent B2
US 8,481,366 · App. 13/094,668 · Granted Jul 9, 2013

Semiconductor device and manufacturing method therefor

Inventors: Masahiko Harayama (Kanagawa, JP); Kouichi Meguro (Kanagawa, JP); Junichi Kasai (Kanagawa, JP)
Assignee: Spansion LLC
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Quick Facts
Patent No.
US 8,481,366
App. No.
13/094,668
Granted
Jul 9, 2013
Kind
B2
Abstract

A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole.

Claims (22)

1. A method for manufacturing a semiconductor device, comprising:

electrically coupling a through electrode and a semiconductor chip with each other; and

forming a resin section that molds the semiconductor chip, so that the through electrode extends between a top edge and a bottom edge of an inner surface of a first through-hole that penetrates through the resin section, and so that a cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole.

2. The method of claim 1 further comprising stacking more than one semiconductor device, so that a through electrode of each of the semiconductor devices contacts the other.

3. The method of claim 1 further comprising stacking more than one semiconductor devices and penetrating the cavity provided in each of the semiconductor devices with a conductive pin, so that the conductive pin directly contacts the through electrode.

4. The method of claim 1 further comprising stacking more than one semiconductor devices and penetrating the cavity provided in each of the semiconductor devices with a conductive pin and electrically coupling the conductive pin and the through electrode with each other.

5. A method for manufacturing a semiconductor device package, comprising:

disposing a lead frame on a die;

forming a convex portion in the lead frame;

disposing a semiconductor chip on a mounting surface of the lead frame;

wire bonding the semiconductor chip to the lead frame;

covering the lead frame with a mold compound; and

cutting off a portion of the mold compound to expose the convex portion in the lead frame wherein a through-hole is formed in the semiconductor device package.

6. The method of claim 5 further comprising cutting off a closed end of the convex portion to create an opened portion of the lead frame that is coplanar with the surface of the mold compound.

7. The method of claim 5 further comprising cutting off a closed end of the convex portion to create an opened portion of the lead frame that extends above the mold compound.

8. The method of claim 5 wherein the convex portion is formed in the lead frame using a pressing die.

9. The method of claim 5 wherein the convex portion has a cross section that is narrower at a closed end of the convex portion than at a base of the convex portion.

10. The method of claim 5 wherein the convex portion extends beyond the mold compound.

11. The method of claim 5 wherein the convex portion is flanged.

12. The method of claim 5 wherein the convex portion is U-shaped.

13. The method of claim 5 wherein the convex portion is V-shaped.

14. The method of claim 6 further comprising placing a connecting pin into the opened portion of the lead frame to connect a plurality of semiconductor device packages.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 22, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 041175/0939 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040908/0960 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036055/0276 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
Priority Claims (1)
JP 2007-254537 · Sep 28, 2007 · national
Continuity (2)
Division 12239566 · Sep 26, 2008
Related Publication 20110201152A1 · Aug 18, 2011