Random cache read using a double memory
A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.
1. A non-volatile memory device configured to perform a random multi-page read operation, the memory device comprising:
a core array of non-volatile memory cells configured to store multiple bits of data per cell;
input lines for receiving an indication of the random multi-page read operation, including an identification of a plurality of pages of data that are to be read from the core array;
a volatile memory coupled to the core array and configured to simultaneously process multiple ones of the plurality of pages of data from the core array in a pipelined manner; and
output lines coupled to the volatile memory and configured to output the pages of data from the non-volatile memory device.
2. The device of claim 1 , wherein the volatile memory includes a main memory coupled to the core array and a cache memory coupled to the output lines.
3. The device of claim 2 , wherein the main memory and the cache memory include static random access memory (SRAM) cells.
4. The device of claim 1 , wherein the core array includes SONOS-type Flash memory cells.
5. The device of claim 1 , further including:
I/O buffers coupled between the volatile memory and the output lines.
6. The device of claim 1 , wherein each of the plurality of pages of data includes a plurality of bytes of data stored proximate to one another in the core array.
7. The device of claim 6 , wherein each of the plurality of pages of data includes approximately 2 KBytes of data.
8. A memory device comprising:
a core array of non-volatile memory cells, each of the non-volatile memory cells being configured to store multiple bits of data;
a first output memory coupled to the core array and configured to receive pages of data from the core array; and
a second output memory coupled to the first output memory and configured to receive the pages of data from the first output memory,
wherein the core array, the first output memory, and the second output memory are configured to perform a page transfer of a first page of data between the core array, the first output memory, and the second output memory in a first pipeline stage while simultaneously performing a page transfer of a second page of data from the second output memory and off of the memory device in a second pipeline stage.
9. The device of claim 8 , further comprising:
an output buffer connected to the second output memory, the second pipeline stage including transferring the second page of data between the second output memory and the output buffer for output from the memory device.
10. The device of claim 9 , wherein the page transfer of the first page of data between the first core array and the first output memory in the first pipeline stage requires about 25 μs, the page transfer of the second page of data between the first output memory and the second output memory in the second pipeline stage requires about 300 ns, and the page transfer of the second page of data between the second output memory and the output buffer in the second pipeline stage requires about 21 μs.
11. The device of claim 8 , wherein the first and second output memories include volatile memory.
12. The device of claim 8 , wherein the core array includes SONOS-type Flash memory cells.
13. The device of claim 12 , wherein the SONOS-type Flash memory cells are configured to store multiple bits of data per cell.
14. The device of claim 8 , wherein the first and second pages of data each include a plurality of bytes of data stored proximate to one another in the core array.
15. The device of claim 14 , wherein each of the first and second pages includes approximately 2 KBytes of data.
16. A non-volatile memory device comprising:
input address lines for receiving addresses that are to be read from the memory device;
a core array of non-volatile SONOS-type Flash memory cells configured to store multiple bits of data per cell;
address decoders coupled to the input address lines and the core array of non-volatile memory cells;
a first output memory coupled to the core array and configured to receive pages of data from the core array;
a second output memory coupled to the first output memory and configured to receive the pages of data from the first output memory, the second output memory receiving the pages of data in a pipelined manner relative to the pages of data received by the first output memory;
I/O buffers coupled to the second output memory; and
output lines coupled to the I/O buffers and configured to output the pages of data from the memory device.
17. The memory device of claim 16 , wherein the first and second output memories include volatile memories.