Patent Assignment
Reel/Frame 036039/0406
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-06-30
Received: 2015-06-30
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(50)
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
App. No. 11/977,034
→
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
App. No. 11/878,296
→
PLL FREQUENCY SYNTHESIZER
App. No. 11/714,139
→
LEVEL CONVERSION CIRCUIT
App. No. 11/650,485
→
REPETITIVE ERASE VERIFY TECHNIQUE FOR FLASH MEMORY DEVICES
App. No. 11/615,710
→
MEMORY DEVICE WITH ACTIVE LAYER OF DENDRIMERIC MATERIAL
App. No. 11/642,477
→
SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR
App. No. 11/636,111
→
METHOD OF FABRICATING METAL-INSULATOR-METAL (MIM) DEVICE WITH STABLE DATA RETENTION
App. No. 11/633,942
→
METHOD AND APPARATUS FOR SECTOR ERASE OPERATION IN A FLASH MEMORY ARRAY
App. No. 11/538,408
→
MEMORY ERASE MANAGEMENT SYSTEM
App. No. 11/470,958
→
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
App. No. 11/494,872
→
NON-VOLATILE MEMORY DEVICE, AND CONTROL METHOD OF NON-VOLATILE MEMORY DEVICE
App. No. 11/479,387
→
AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
App. No. 11/424,934
→
PHASE ADJUSTER CIRCUIT AND PHASE ADJUSTING METHOD
App. No. 11/447,852
→
CIRCUIT FOR ASYNCHRONOUSLY RESETTING SYNCHRONOUS CIRCUIT
App. No. 11/443,110
→
SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREFOR
App. No. 11/443,640
→
METHODS FOR FABRICATING FLASH MEMORY DEVICES
App. No. 11/418,352
→
MEMORY DEVICE AND METHODS FOR ITS FABRICATION
App. No. 11/409,361
→
MULTI MEDIA CARD WITH HIGH STORAGE CAPACITY
App. No. 11/400,902
→
METHODS FOR ERASING AND PROGRAMMING MEMORY DEVICES
App. No. 11/399,130
→
OXYGEN ELIMINATION FOR DEVICE PROCESSING
App. No. 11/371,023
→
RECESSED CHANNEL WITH SEPARATED ONO MEMORY DEVICE
App. No. 11/361,277
→
DC-DC CONVERTER AND ITS CONTROL METHOD, AND SWITCHING REGULATOR AND ITS CONTROL METHOD
App. No. 11/350,720
→
METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE
App. No. 11/341,029
→
METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
App. No. 11/340,916
→
CARRIER FOR STACKED TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING STACKED TYPE SEMICONDUCTOR DEVICES
App. No. 11/341,984
→
RANDOM CACHE READ USING A DOUBLE MEMORY
App. No. 11/332,241
→
MICROCOMPUTER, METHOD OF CONTROLLING CACHE MEMORY, AND METHOD OF CONTROLLING CLOCK
App. No. 11/299,893
→
MEMORY ARRAY TESTER INFORMATION PROCESSING SYSTEM
App. No. 11/253,521
→
METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE
App. No. 11/244,166
→
HIGH PERFORMANCE FLASH MEMORY DEVICE CAPABLE OF HIGH DENSITY DATA STORAGE
App. No. 11/229,527
→
MULTI-BIT FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM RATE
App. No. 11/229,519
→
METHOD AND APPARATUS FOR INITIALIZATION CONTROL IN A NON-VOLATILE MEMORY DEVICE
App. No. 11/194,111
→
VOLTAGE CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE
App. No. 11/166,575
→
SEMICONDUCTOR DEVICE AND ITS CONTROL METHOD
App. No. 11/127,713
→
RESET CONTROL CIRCUIT AND RESET CONTROL METHOD
App. No. 11/063,975
→
MEMORY ELEMENT USING ACTIVE LAYER OF BLENDED MATERIALS
App. No. 11/052,688
→
SIGMADELTA MODULATOR FOR PLL CIRCUIT
App. No. 11/042,136
→
CURRENT SENSING ARCHITECTURE FOR HIGH BITLINE VOLTAGE, RAIL TO RAIL OUTPUT SWING AND VCC NOISE CANCELLATION
App. No. 11/023,914
→
METHOD OF PROGRAMMING, READING AND ERASING MEMORY-DIODE IN A MEMORY-DIODE ARRAY
App. No. 11/021,958
→
UTILIZATION OF MEMORY-DIODE WHICH MAY HAVE EACH OF A PLURALITY OF DIFFERENT MEMORY STATES
App. No. 11/021,944
→
HIGH-VOLTAGE TRANSISTOR HAVING A U-SHAPED GATE AND METHOD FOR FORMING SAME
App. No. 11/003,528
→
MEMORY DEVICE WITH A SELECTION ELEMENT AND A CONTROL LINE IN A SUBSTANTIALLY SIMILAR LAYER
App. No. 11/001,519
→
CONTROL OF MEMORY DEVICES POSSESSING VARIABLE RESISTANCE CHARACTERISTICS
App. No. 10/983,919
→
SYSTEM AND METHOD FOR PROTECTING SEMICONDUCTOR DEVICES
App. No. 10/976,816
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SERIAL COMMUNICATION DEVICE
App. No. 10/899,072
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APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
App. No. 10/896,292
→
FLASH MEMORY WITH HIGH-K DIELECTRIC MATERIAL BETWEEN SUBSTRATE AND GATE
App. No. 10/658,936
→
SHALLOW TRENCH ISOLATION APPROACH FOR IMPROVED STI CORNER ROUNDING
App. No. 10/277,395
→
ABNORMALITY DETECTION DEVICE FOR DETECTING AN ABNORMALITY IN A COMMUNICATION BUS
App. No. 09/778,837
→