Current sensing architecture for high bitline voltage, rail to rail output swing and Vcc noise cancellation
View Patent ↗The present invention pertains to a circuit arrangement that, in one example, facilitates reading or determining an amount of current that flows through a memory cell when one or more voltages are applied to the cell. The amount of current resulting from the applied voltages is a function of the amount of charge stored within the cell, among other things, and the amount of stored charge represents information stored within the cell. As such, reading the resulting current allows data stored within the cell to be accessed and retrieved. It will be appreciated however, that use of the circuitry disclosed herein is not limited to memory applications. Rather, it can be used in any application where current sensing is required along with a regulated supply voltage.
1. A circuit for sensing a core current flowing through a bitline path and a memory cell in response to voltages applied to a gate of the cell and an acting drain of the cell, the magnitude of the core current also being a function of the amount of charge stored within the cell, the circuit comprising:
a differential amplifier component operatively coupled to the bitline path and configured to provide a substantially constant desired voltage to a desired voltage node on the bitline path where the bitline path is operatively coupled to the acting drain of the cell; and
a post processing circuit component operatively coupled to the bitline path and configured to receive an Rsense voltage that is a function of the core current and further configured to output an output voltage (SAIN) that is indicative of the core current, but is an amplification of the Rsense voltage,
the post processing circuit component comprising:
a level shifter component operatively coupled to the bitline path and configured to shift the Rsense voltage; and
a common source gain component operatively coupled to the level shifter component and configured to receive the shifted Rsense voltage and to amplify the same to produce the output voltage.
2. A circuit for sensing a core current flowing through a bitline path and a memory cell in response to voltages applied to a gate of the cell and an acting drain of the cell, the magnitude of the core current also being a function of the amount of charge stored within the cell, the circuit comprising:
a differential amplifier component operatively coupled to the bitline path and configured to provide a substantially constant desired voltage to a desired voltage node on the bitline path where the bitline path is operatively coupled to the acting drain of the cell; and
a post processing circuit component operatively coupled to the bitline path and configured to receive an Rsense voltage that is a function of the core current and further configured to output an output voltage (SAIN) that is indicative of the core current, but is an amplification of the Rsense voltage, the post processing circuit comprising:
a level shifter component operatively coupled to the bitline path and configured to shift the Rsense voltage; and
a common source gain component operatively coupled to the level shifter component and configured to receive the shifted Rsense voltage and to amplify the same to produce the output voltage,
wherein the level shifter component comprises a source follower transistor that level shifts the Rsense voltage.
3. The circuit of claim 2 , wherein a gate of the source follower transistor receives the Rsense voltage.
4. The circuit of claim 2 , wherein a source of the source follower transistor outputs the shifted Rsense voltage.
5. The circuit of claim 2 , wherein the source follower transistor is an NMOS transistor.
6. The circuit of claim 2 , wherein the common source gain component comprises a gain transistor and a gain resistor Rgain, where the amplification of the common source gain component is equal to the transconductance (Gm) of the gain transistor multiplied by the value of the gain resistor, and where the output voltage of the common source gain component can be taken at a drain of the gain transistor.
7. The circuit of claim 2 , wherein the common source gain component comprises a gain transistor and a tunable transistor, where the amplification of the common source gain component is equal to the transconductance (Gm) of the gain transistor multiplied by a resistance value (Ro) of the tunable transistor as seen looking into a drain of the tunable transistor, where Ro can be adjusted by controlling a bias voltage applied to a gate of the tunable transistor, and where the output voltage of the common source gain component can be taken at a drain of the gain transistor.
8. The circuit of claim 6 , wherein at least one of:
a gate of the gain transistor receives the shifted Rsense voltage;
the gain transistor comprises a PMOS transistor;
the gain resistor has a value of between about 15000 ohms to about 30000 ohms;
the output voltage (SAIN) from the post processing circuit component can swing from between about 0 volts to about a supply voltage (Vcc); and
available current in output node (SAIN) from the post processing circuit component can be much larger than the memory cell current—thus resulting in a faster output settling down speed.
9. The circuit of claim 8 , wherein a sense resistor Rsense is included in the bitline path for developing the Rsense voltage.
10. The circuit of claim 9 , wherein at least one of:
the sense resistor has a value of between about 3000 ohms to about 5000 ohms; and
the Rsense voltage is between about 50 millivolts to about 150 millivolts.
11. The circuit of claim 9 , wherein the differential amplifier component is operatively coupled to the bitline path via a bitline transistor within the bitline path.
12. The circuit of claim 11 , wherein at least one of:
the bitline transistor is an NMOS transistor; and
a gate of the bitline transistor is operatively coupled to the differential amplifier, a drain of the bitline transistor is coupled to the sense resistor Rsense so as to receive the Rsense voltage and a source of the bitline transistor is coupled to the desired voltage node.
13. The circuit of claim 12 , wherein the differential amplifier component comprises:
a left branch; and
a right branch,
where the left and right branches are in parallel with one another,
where the left branch includes a left resistor and a left transistor in series with one another,
where the right branch includes a right resistor and a right transistor in series with one another,
where the gate of the bitline transistor is coupled to the left branch of the differential amplifier between the left resistor and the left transistor,
where a gate of the left transistor is coupled to the desired voltage node,
where a gate of the right transistor is coupled to reference voltage about which the differential amplifier component modulates the desired voltage at the desired voltage node, and
where a source of the left transistor and a source of the right transistor are coupled to a drain of a bias transistor, a source of which is coupled to ground.
14. The circuit of claim 13 , wherein the level shifter component further comprises:
a secondary transistor, a gate of which is coupled to a gate of the bias transistor, a source of which is coupled to ground and a drain of which is coupled to a source of the source follower transistor so as to receive the shifted Rsense voltage.
15. The circuit of claim 14 , wherein the common source gain component further comprises:
a source degeneration resistor operatively coupled to a source of the gain transistor and designed to mitigate noise introduced to the circuit through a source of power.
16. The circuit of claim 15 , wherein the differential amplifier component, sense resistor in the bitline path, level shifter component and common source gain component are coupled to at least one of a supply voltage Vcc and respective power down (PD) transistors.
17. The circuit of claim 13 , further comprising:
a bootstrapping component situated between the differential amplifier and the bitline path and operable to compensate for a threshold voltage drop across the bitline transistor, the bootstrapping component comprising:
a bootstrapping capacitor, a left end of which is coupled to the gate of the bitline transistor, and a right end of which is coupled to the left branch of the differential amplifier between the left resistor and the left transistor, where the right end of the bootstrapping capacitor is coupled to ground and the left end of the bootstrapping capacitor is coupled to a reference voltage VtREF when a power down (PD) signal is applied to the circuit, where VtREF is at or close to a threshold voltage value of the bitline transistor.
18. The circuit of claim 17 , wherein the bootstrapping component further comprises:
an NMOS transistor, a drain of which is coupled to the right end of the bootstrapping capacitor, a source of which is coupled to ground and a gate of which is coupled to a power down (PD) signal input such that the right end of the bootstrapping capacitor is coupled to ground upon application of a power down (PD) signal; and
a CMOS pass gate coupled to the left end of the bootstrapping capacitor and the VtREF voltage, and configured to couple the gate of the bitline transistor to VtREF upon application of a (PD) signal.
19. The circuit of claim 18 , wherein the CMOS pass gate comprises:
a PMOS initializing transistor, a drain of which is coupled to the left end of the bootstrapping capacitor, a source of which is coupled to VtREF and a gate of which is coupled to an inverse power down signal input; and
an NMOS initializing transistor, a drain of which is coupled to VtREF and the source of the PMOS initializing transistor, a source of which is coupled to the left end of the bootstrapping capacitor and the drain of the PMOS initializing transistor and a gate of which is coupled to a power down signal input.
20. The circuit of claim 18 , where after the circuit comes out of a power down state, the bootstrapping capacitor facilitates applying a voltage of a supply voltage (Vcc) plus VtREF onto the desired voltage node.
21. The circuit of claim 16 , where noise from the supply voltage Vcc is cancelled by being applied substantially equally to the gate (G) of the gain transistor of the common source gain component and the source (S) of the gain transistor of the common source gain component.
22. A circuit for sensing a core current flowing through a bitline path and a multi-level memory cell in response to voltages applied to a gate of the cell and an acting drain of the cell, the magnitude of the core current also being a function of the amount of charge stored within the cell, the circuit comprising:
a post processing circuit component operatively coupled to the bitline path and configured to receive a level shifted Rsense voltage that is a function of the core current and further configured to output an output voltage (SAIN) that is indicative of the core current, but is an amplification of the Rsense voltage, the Rsense voltage being generated in the bitline path, and the multi-level cell configured to store three or more states such that the output voltage (SAIN) is indicative of one of the three or more possible states of the multi-level memory cell.