Granted Patent B2

US 7,450,419 · App. 11/636,111 · Granted Nov 11, 2008

Abstract

Claims (77)

1. A semiconductor device comprising:

a memory cell array comprising a plurality of nonvolatile memory cells;

a detection circuit detecting a number of bits to be written as division data that is divided from data to be programmed into the memory cell array and comparing the number of bits with a predetermined number of bits;

a latch circuit latching inversion data, which is either the division data inverted or not inverted in accordance with a result of comparing the number of bits with the predetermined number of bits, wherein the latch circuit includes a pair of nodes operating in a complementary manner, and latches the inversion data that is either the division data inverted or not inverted by inputting the division data into either of the pair of nodes in accordance with the result of comparing the number of bits with the predetermined number of bits;

a write circuit coupled to the latch circuit and programming the inversion data into the memory cell array; and

a control circuit coupled to the detection circuit, the latch circuit, and the write circuit to cause the detection circuit to detect the number of bits to be written as next division data and to compare the number of bits of the next division data with the predetermined number of bits, while concurrently controlling the write circuit to program the inversion data into the memory cell array.

2. The semiconductor device as claimed in claim 1 , further comprising an index latch circuit latching index data indicative of whether the inversion data is the division data inverted or not inverted,

wherein the detection circuit outputs the index data to the index latch circuit in response to the result of comparing the number of bits with the predetermined number of bits; and

wherein the write circuit programs the index data from the index latch circuit into the memory cell array, while programming the inversion data into the memory cell array.

3. The semiconductor device as claimed in claim 2 , further comprising a switch circuit transferring the inversion data to the latch circuit;

wherein the switch circuit is switched off, while the detection circuit is detecting the number of bits to be written as the division data and comparing the number of bits with the predetermined number of bits, and the switch circuit is switched on, while transferring the inversion data to the latch circuit.

4. The semiconductor device as claimed in claim 3 , further comprising a storage device storing the data to be programmed, the data being received from an external circuit, and outputting the division data to the detection circuit and the latch circuit.

5. The semiconductor device as claimed in claim 4 ,

wherein the write circuit pre-charges a bit line to be connected to one of the plurality of memory cells in the memory cell array, into which the inversion data is to be programmed, before programming the inversion data into the memory cell array, and

wherein the control circuit controls the detection circuit to detect the number of bits to be written as next division data and to compare the number of bits of the next division data with the predetermined number of bits, while the write circuit is precharging the bit line.

6. A semiconductor device comprising:

a memory cell array comprising a plurality of nonvolatile memory cells;

a detection circuit detecting a number of bits to be written as division data that is divided from data to be programmed into the memory cell array and comparing the number of bits with a predetermined number of bits;

a latch circuit latching inversion data, which is either the division data inverted or not inverted in accordance with a result of comparing the number of bits with the predetermined number of bits; and

a write circuit coupled to the latch circuit and programming the inversion data into the memory cell array,

wherein the latch circuit includes a pair of nodes operating in a complementary manner, and latches the inversion data that is either the division data inverted or not inverted by inputting the division data into either of the pair of nodes in accordance with the result of comparing the number of bits with the predetermined number of bits.

7. The semiconductor device as claimed in claim 6 ,

wherein the latch circuit further includes a circuit having two inverter circuits connected circularly; and

wherein each of the pair of nodes is respectively arranged between the two inverter circuits.

8. A method for controlling a semiconductor device comprising a memory cell array having a plurality of nonvolatile memory cells, the method comprising:

detecting a number of bits to be written as division data that is divided from data to be programmed into the memory cell array;

comparing the number of bits with a predetermined number of bits;

inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits; and

programming the inversion data into the memory cell array,

wherein the inverting or not inverting the division data is performed using a latch circuit which comprises a pair of nodes operating in a complementary manner, and latches the inversion data that is either the division data inverted or not inverted by inputting the division data into either of the pair of nodes in accordance with the result of comparing the number of bits with the predetermined number of bits.

9. A wireless communications device, comprising:

a flash memory comprising:

a memory cell array;

a bit detection portion for detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array;

a bit comparison portion for comparing the detected number of bits with a predetermined number of bits;

an inversion portion for inverting the division data to produce inversion data in accordance with a result of comparing the detected number of bits with the predetermined number of bits; and

a programming portion for programming the inversion data into the memory cell array;

wherein the bit detection portion is further operable to detect the number of bits to be written as next division data, the bit comparison portion is further operable to compare the number of bits of next division data with the predetermined number of bits, and the inversion portion includes a pair of nodes operating in a complementary manner, and latches the inversion data that is either the division data inverted or not inverted by inputting the division data into either of the pair of nodes in accordance with the result of comparing the number of bits with the predetermined number of bits while the programming portion is concurrently programming the inversion data into the memory cell array;

a processor;

a communications component;

a transmitter;

a receiver; and

an antenna connected to the transmitter circuit and the receiver circuit.

10. The wireless communications device of claim 9 , wherein said flash memory is NAND flash memory.

11. The wireless communications device of claim 9 , wherein said flash memory is NOR flash memory.

12. The wireless communications device of claim 9 , wherein said flash memory comprises at least one memory cell operable to store more than one bit.

13. A computing device comprising:

a processor;

an input component;

an output component; and

a memory comprising:

a volatile memory; and

a flash memory comprising:

a memory cell array;

a bit detection portion for detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array;

a bit comparison portion for comparing the detected number of bits with a predetermined number of bits;

an inversion portion for inverting the division data to produce inversion data in accordance with a result of comparing the detected number of bits with the predetermined number of bits; and

a programming portion for programming the inversion data into the memory cell array;

wherein the bit detection portion is further operable to detect the number of bits to be written as next division data, the bit comparison portion is further operable to compare the number of bits of next division data with the predetermined number of bits, and the inversion portion includes a pair of nodes operating in a complementary manner, and latches the inversion data that is either the division data inverted or not inverted by inputting the division data into either of the pair of nodes in accordance with the result of comparing the number of bits with the predetermined number of bits while the programming portion is concurrently programming the inversion data into the memory cell array.

14. The computing device of claim 13 , wherein said computing device is a personal computer (PC).

15. The computing device of claim 13 , wherein said computing device is a personal digital assistant (PDA).

16. The computing device of claim 13 , wherein said computing device is a gaming system.

17. A portable media player comprising:

a processor;

a cache;

a user input component;

a coder-decoder component; and

a memory comprising:

a flash memory comprising:

a memory cell array;

a bit detection portion for detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array;

a bit comparison portion for comparing the detected number of bits with a predetermined number of bits;

an inversion portion for inverting the division data to produce inversion data in accordance with a result of comparing the detected number of bits with the predetermined number of bits; and

a programming portion for programming the inversion data into the memory cell array;

wherein the bit detection portion is further operable to detect the number of bits to be written as next division data, the bit comparison portion is further operable to compare the number of bits of next division data with the predetermined number of bits, and the inversion portion includes a pair of nodes operating in a complementary manner, and latches the inversion data that is either the division data inverted or not inverted by inputting the division data into either of the pair of nodes in accordance with the result of comparing the number of bits with the predetermined number of bits while the programming portion is concurrently programming the inversion data into the memory cell array.

18. The portable media player of claim 17 , wherein said portable media player is a portable music player.

19. The portable media player of claim 17 , wherein said portable media player is a portable video player.

Assignments (8)