High-voltage transistor having a U-shaped gate and method for forming same
View Patent ↗According to one exemplary embodiment, a method includes forming first, second, and third shallow trench isolation regions in a substrate, wherein the second shallow trench isolation region is situated between the first and the third shallow trench isolation regions. The second shallow trench isolation region is removed to form a transistor channel trench. A substantially U-shaped gate is formed in the transistor channel trench. According to another embodiment, a transistor includes a substrate, and first and second shallow trench isolation regions in the substrate. A substantially U-shaped gate is formed in the substrate between said first and second shallow trench isolation regions.
1. A transistor comprising:
a substrate;
first and second shallow trench isolation regions in said substrate;
a substantially U-shaped trench situated in said substrate between said first and second shallow trench isolation regions;
a substantially U-shaped gate situated in said substantially U-shaped trench;
first and second lightly doped drain (LDD) implant regions situated on opposite sides of said gate;
a channel situated below said gate, said channel having a channel length extending substantially from a first diffusion edge of said first LDD implant region to a second diffusion edge of said second LDD implant region;
first and second spacers situated on opposite sides of said gate and situated over said substrate;
first and second source/drain regions situated in said substrate;
a first silicide layer situated on said first source/drain region and situated in alignment with said first spacer and a second silicide layer situated on said second source/drain region and situated in alignment with said second spacer.
2. The transistor of claim 1 wherein said substantially U-shaped gate is adjacent to an overlap region in a substantially y-axis direction.
3. The transistor of claim 1 , wherein said transistor exhibits an increased value of BVdss.
4. The transistor of claim 1 wherein said transistor exhibits an increased punch-through voltage.
5. The transistor of claim 1 further comprising a silicide layer on said gate.
6. The transistor of claim 1 wherein said gate has a decreased size for a given channel length.