Method of determining voltage compensation for flash memory devices
View Patent ↗The present invention determines or identifies programming variations for different groups within an array or memory device that properly program memory cells within the respective groups. Then, during programming operations for a given memory cell, programming voltages are applied according to the determined or identified programming variations for the group to which the given memory cell belongs. These adjusted programming variations facilitate successful programming of the particular memory cell.
1. A method of programming a memory cell comprising:
establishing a plurality of groups of memory cells associated with a memory cell array, wherein each group has a predetermined set of program voltages associated therewith, wherein at least two groups in the memory cell array have a different predetermined set of program voltages;
identifying the group of the plurality of groups of memory cells that the memory cell is a member of;
obtaining the predetermined set of program voltages associated with the identified group, wherein the predetermined set of program voltages include nominal and adjustment values, and wherein the adjustment values include a gate voltage adjustment value; and
programming the memory cell with the obtained program voltages.
2. The method of claim 1 , further comprising verifying the programming of the memory cell.
3. The method of claim 1 , wherein the group is comprised of memory cells having similar programming properties.
4. The method of claim 1 , wherein the adjustment values include a drain voltage adjustment value.
5. The method of claim 1 , wherein the adjustment values include a source voltage adjustment value.
6. A method of programming a memory cell comprising:
identifying a group that the memory cell is a member of;
obtaining program voltages associated with the identified group, wherein the program voltages include nominal and adjustment values, and wherein the adjustment values include a drain voltage adjustment value, and wherein obtaining the drain voltage adjustments for an identified group of memory cells comprises:
determining drain voltage adjustments for at least a portion of memory cells of the device;
segmenting the memory cells of the device into the number of groups according to programming properties, wherein the programming properties include the determined drain voltage adjustments; and
selecting group drain voltage adjustments for the number of groups that allow programming of memory cells within the groups; and
programming the memory cell with the obtained program voltages.
7. The method of claim 6 , wherein determining drain voltage adjustments comprises characterizing the dual bit memory cell and analyzing resulting data.
8. The method of claim 6 , wherein segmenting the memory cells of the device according to programming properties includes segmenting according to distance from bitline contacts.
9. The method of claim 6 , wherein segmenting the memory cells of the device according to programming properties includes segmenting according to distance from a power source.
10. The method of claim 6 , wherein selecting group drain voltage adjustments comprises determining an average drain voltage adjustment for memory cells within respective groups.
11. The method of claim 6 , wherein segmenting the memory cells of the device according to programming properties includes segmenting according to selected ranges of expected and actual drain voltage adjustments.
12. The method of claim 11 , wherein the expected drain voltage adjustments are based on the actual drain voltage adjustments of memory cells having a substantially similar location with respect to bitline contacts.
13. The method of claim 1 , wherein the memory cells in each group are associated with a similar memory cell programming characteristic.
14. The method of claim 13 , wherein the similar memory cell programming characteristic comprises a similar distance of the memory cells to contacts within the memory cell array.
15. The method of claim 13 , wherein the similar memory cell programming characteristic comprises a similar distance of the memory cells to a power source.
16. The method of claim 13 , wherein the similar memory cell programming characteristic comprises a similar location within the array of memory of memory cells.