IP Library Granted Patent US 7,387,936
Granted Patent B2
US 7,387,936 · App. 11/977,034 · Granted Jun 17, 2008

Semiconductor device and method of fabricating the same

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Quick Facts
Patent No.
US 7,387,936
App. No.
11/977,034
Granted
Jun 17, 2008
Kind
B2
Abstract

A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The oxide film has first portions related to the bit areas and a second portion that is located between the bit areas and is thicker than the first potions. The first portions serve as tunneling oxide portions, while the second portion allows reduced tunneling.

Claims (11)

1. A method of fabricating a semiconductor device comprising the steps of:

(a) forming a tunneling oxide film having a uniform thickness on a substrate;

(b) forming a pair of first diffused regions in the substrate;

(c) forming a surface protection film provided on the tunneling oxide film and located above the pair of first diffused regions; and

(d) re-oxidizing the tunneling oxide film exposed through the surface protection film so that the tunneling oxide film has a self-aligned portion having a thickness that allows reduced tunneling of charges.

2. The method as claimed in claim 1 , wherein the steps (a) and (d) comprise a thermal or plasma oxidization process.

3. The method as claimed in claim 1 , further comprising a step (e) of forming a second diffused region that is located between the pair of first diffused regions and extends vertically from a surface of the surface on which the tunneling oxide film is formed.

4. The method as claimed in claim 3 , wherein the step (e) uses sidewalls of the surface protection film so that the second diffused region is self-aligned.

5. The method as claimed in claim 3 , wherein the step (e) forms the second diffused region by ion implantation.

6. The method as claimed in claim 1 , wherein the step (b) comprises a step of forming a patterned resist having windows to which sidewalls are provided, so that the pair of first diffused regions is self-aligned using the sidewalls.

7. The method as claimed in claim 6 , wherein the step (b) forms the pair of first diffused regions by ion implantation.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036039/0406 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →