Methods for erasing and programming memory devices
View Patent ↗A dual-bit memory device includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions to erase the charge storage regions. Other techniques for programming a memory can be provided in which holes can be injected into at least one of the charge storage regions to program the charge storage regions.
1. A method, comprising:
providing a memory comprising a first charge storage region spaced apart from a second charge storage region by an isolation region, a gate and a substrate comprising a buried junction region; and
programming the memory by injecting holes into the at least one of the charge storage regions to neutralize electrons in the at least one of the charge storage regions by applying a negative voltage to the gate and a positive voltage to the buried junction region.
2. A method according to claim 1 , further comprising:
injecting electrons into at least one of the charge storage regions via Fowler-Nordheim (FN) tunneling to erase the at least one charge storage region.
3. A method according to claim 2 , wherein Fowler-Nordheim (FN) tunneling comprises:
grounding the substrate;
applying a positive voltage to the gate to pull electrons from the substrate to the at least one of the charge storage regions.
4. A method according to claim 1 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
5. A method according to claim 1 , wherein the isolation region and at least one of the charge storage regions are substantially charge free after programming.
6. A method according to claim 5 , wherein the isolation region and at least one of the charge storage regions are substantially charge free after programming such that substantially no residual electrons remain in the isolation region following programming.
7. A method according to claim 2 , electrons are only injected into the at least one of the charge storage regions.
8. A semiconductor device, comprising:
a substrate comprising a buried junction region;
a gate;
an isolation region;
a first charge storage region;
a second charge storage region spaced apart from the first charge storage region by the isolation region, wherein at least one of the charge storage regions is configured to be programmed by injecting holes into the at least one of the charge storage regions to neutralize electrons in the at least one of the charge storage regions by applying a negative voltage to the gate and a positive voltage to the buried junction region.
9. A semiconductor device according to claim 8 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
10. A semiconductor device according to claim 8 , wherein holes are only injected into the charge storage regions.
11. In a memory comprising a first charge storage region spaced apart from a second charge storage region by an isolation region, a substrate having a buried junction region, and a gate, wherein at least one of the charge storage regions hold electrons, a method comprising:
injecting holes into at least one of the charge storage regions by: applying a positive voltage to the buried junction region; and applying a negative voltage to the gate to program at least one of the charge storage regions by injecting holes from the buried junction region into the at least one of the charge storage regions to neutralize electrons in the at least one of the charge regions.
12. A method according to claim 11 , further comprising:
injecting electrons into at least one of the charge storage regions to erase the at least one charge storage region.
13. A method according to claim 12 , wherein injecting electrons into at least one of the charge storage regions to erase the at least one charge storage region of the memory, comprises
Fowler-Nordheim (FN) tunneling electrons into at least one of the charge storage regions to erase the at least one of the charge storage regions.
14. A method according to claim 13 , wherein the memory further comprises a substrate and a gate, and wherein Fowler-Nordheim (FN) tunneling comprises:
grounding the substrate; and
applying a positive voltage to the gate to pull electrons from the substrate into the at least one of the charge storage regions to erase the at least one charge storage region.
15. A method according to claim 12 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
16. A method according to claim 12 , electrons are only injected into the at least one of the charge storage regions.
17. A method according to claim 11 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
18. A method according to claim 17 , wherein the isolation region and charge storage regions are substantially charge free after programming such that substantially no residual holes remain in the isolation region following programming.
19. A method according to claim 18 , holes are only injected into the charge storage regions.