Internally derived address generation system and method for burst loading of a synchronous memory
View Patent ↗An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory device. The burst-block starting address can be stored in the mirror register and output from a selector circuit, such as a multiplexer, when that address is chosen. Otherwise, the multiplexer can simply perform its normal operation of selecting between an address pointed to by a counter, the external address, or the incremented counter output, based on the state of the external counter control signals. The system includes a mirror register, a counter, and a multiplexer that selects either the mirror register stored address or the internally processed address.
1. A memory controller comprising:
a counter configured to receive a base address via an external bus system and to perform a count operation beginning at the base address received by the counter; and
a mirror address generator configured to provide a mirror address to the counter via an internal bus system, exclusive of the external bus system, wherein the base address is a first memory address and the mirror address is a second memory address,
the counter configured to receive the mirror address responsive to a counter reinitialize command, and to perform a further count operation beginning at the received mirror address.
2. The memory controller as recited in claim 1 , wherein the mirror address generator is configured to generate the mirror address in response to at least one of a counter load command and a counter reset command, and to forward the mirror address to a mirror register to be stored by the mirror register.
3. The memory controller as recited in claim 1 , wherein the mirror address generator is configured to generate the mirror address including all logic zeros in response to a counter reset command and the counter is reinitialized to the mirror address that contains the all logic zeros.
4. The memory controller as recited in claim 1 , wherein the base address is user loaded.
5. The memory controller as recited in claim 1 , wherein the memory controller is communicatively coupled with a synchronous memory, the synchronous memory configured to be written to or read from a non-masked addresses of the synchronous memory based on sequential transitions of a clocking signal.
6. The memory controller as recited in claim 5 , wherein the synchronous memory includes a multi-port memory, wherein one port of the multi-port memory is configured to receive output from a memory address decoder.
7. A system comprising:
a random access memory (RAM) including a plurality of memory cells, each memory cell identifiable through a memory address;
a processing system communicatively coupled with the RAM and configured to access a block of memory cells, of the plurality of memory cells; and
a memory controller communicatively coupled with the RAM and the processing system, the memory controller including:
a burst counter configured to receive a load address from the processing system via an external bus system and to perform a counting operation beginning at the load address received from the processing system; and
a mirror address generator configured to generate a mirror address responsive to at least one of a counter load command and counter reset command and to cause the mirror address to be stored in a mirror register, wherein the load address is a first memory address and the mirror address is a second memory address, the burst counter configured to:
receive, responsive to a counter reinitialize command, the mirror address from the mirror register via an internal bus system, exclusive of the external bus system; and
perform a further counting operation beginning at the received mirror address.
8. The system as recited in claim 7 , wherein the burst counter, responsive to the reinitialize command is configured to retransmit beginning at the mirror address subsequent to the counting operation, wherein the mirror address generated by the mirror address generator is the load address.
9. The system as recited in claim 8 , wherein the mirror address generator is configured to generate a mirror address that includes all logic zero values, responsive to the counter reset command.
10. The system as recited in claim 8 , wherein the burst counter, responsive to the reinitialize command is configured to retransmit beginning at the mirror address containing the all logic zero values, subsequent to the counting operation.
11. The system as recited in claim 7 , wherein the counting operation performed by the burst counter includes incrementing or decrementing beginning with at least one of the load address and the mirror address.
12. The system as recited in claim 7 , further comprising:
a mask register configured to store masked addresses, wherein the burst counter is configured to receive the masked addresses and to increment at least one of the load address and the mirror address to a next non-masked address.