Select transistor using buried bit line from core
View Patent ↗A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.
1. A semiconductor device comprising:
a core memory array area including a plurality of memory cells and a plurality of bit lines; and
a periphery area including a plurality of select transistors, the plurality of select transistors being formed at substantially a same pitch as the memory cells in the core memory array area and with substantially a same channel length as the memory cells in the core memory array area, select bit lines of the plurality of bit lings extending from the core memory array area to the periphery area,
where a distance exists between a non-select bit line and the periphery area, the distance ranging from about 0 Å to about 10,000 Å.
2. The semiconductor device of claim 1 wherein each of the select bit lines functions as a source or drain for one of the plurality of select transistors.
3. The semiconductor device of claim 1 wherein the periphery area includes a same channel oxide as the core memory array area.
4. The semiconductor device of claim 3 wherein the channel oxide includes an oxide-nitride-oxide stack.
5. The semiconductor device of claim 1 wherein a channel oxide of the core memory array area includes an oxide-nitride-oxide stack and a channel oxide of the periphery area includes a nitride-oxide stack.
6. The semiconductor device of claim 1 wherein a channel oxide of the core memory array area includes an oxide-nitride-oxide stack and a channel oxide of the periphery area includes a periphery oxide.
7. The semiconductor device of claim 1 wherein at least one select transistor in the periphery area is isolated from another select transistor via shallow trench isolation.
8. A semiconductor device comprising:
a core memory array area including a plurality of first bit lines and a plurality of second bit lines; and
a first periphery area located at a first end of the core memory array area; and
a second periphery area located at a second end of the core memory array area, the plurality of first bit lines being extended from the core memory array area to the first periphery area, the plurality of second bit lines being extended from the core memory array area to the second periphery area,
wherein select transistors in the first and second periphery areas have substantially a same pitch as memory cells in the core memory array area, and
wherein a distance between the core memory array area and the first and second periphery areas ranges from about 0 Å to about 10,000 Å.
9. The semiconductor device of claim 8 wherein memory cells in the core memory array area and select transistors in the first periphery area and the second periphery area each include an oxide-nitride-oxide stack.
10. The semiconductor device of claim 8 wherein the core memory array area includes a channel oxide-nitride-oxide stack, and
wherein select transistors in at least one of the first periphery area or the second periphery area include an oxide-nitride stack.
11. The semiconductor device of claim 8 wherein the core memory array area includes an oxide-nitride-oxide stack, and
wherein at least one of the first periphery area or the second periphery area includes an oxide.
12. The semiconductor device of claim 8 wherein bit lines in the core memory array area are alternating extended to the first and second periphery areas.
13. The semiconductor device of claim 8 wherein the first and second periphery areas each includes a plurality of select transistors, the select transistors are isolated from each other using shallow trench isolation.
14. A semiconductor device comprising:
a core memory array area including a plurality of first bit lines and a plurality of second bit lines; and
a periphery area located on a first side of the core memory array area, the plurality of first bit lines being extended from the core memory array area to the periphery area, a distance between the core memory array area and the periphery area ranging from about 0 Å to about 10,000 Å.
15. The semiconductor device of claim 14 further comprising:
a second periphery area located on a second side of the core memory array area, the plurality of second bit lines being extended from the core memory array area to the second periphery area, a distance between the core memory array area and the second periphery area ranging from about 0 Å to about 10,000 Å.
16. The semiconductor device of claim 15 wherein the plurality of first bit lines alternate with the plurality of second bit lines in the core memory array area.
17. The semiconductor device of claim 15 wherein select transistors in the first periphery area and the second periphery area are formed at a same pitch as memory cells of the core memory array area.