Integrated circuit, debugging circuit, and debugging command control method

1. An integrated circuit, comprising:

a bus;

a processing unit configured to execute a user program; and

a debugging circuit coupled to the bus, the debugging circuit comprising a command register,

wherein, when the processing unit executes a command including a break factor in the user program,

the processing unit halts the execution of the user program and makes a command transfer request to the debugging circuit,

the debugging circuit makes a split response for freeing a use right of the bus from the processing unit,

the processing unit frees the use right of the bus and enters a wait state,

the debugging circuit prepares a debugging command in the command register and transfers the debugging command to the processing unit via the bus, and

the processing unit restarts the execution of the halted user program after executing the debugging command,

wherein the debugging circuit is settable in one of a first operation mode in which the split response is made and a second operation mode in which the split response is not made,

in an initial state, a command for branching to a specific address is stored in the command register of the debugging circuit, and

when the debugging circuit is set in the second operation mode, the debugging circuit immediately transfers the command for branching to the specific address to the processing unit in response to the command transfer request,

wherein after the processing unit executes the command for branching to the specific address and a command that begins from the specific address, and issues a subsequent command transfer request to the debugging circuit, the debugging circuit makes the split response even when the debugging circuit is set in the second operation mode.

2. The integrated circuit according to claim 1 , further comprising

a memory for storing the user program, the memory being coupled to the bus,

wherein the debugging circuit has a function of accessing the memory via the bus in response to external control.

3. The integrated circuit according to claim 1 ,

wherein the split response indicates that the debugging circuit is in preparation for a response.

4. The integrated circuit according to claim 1 , wherein, when a desired command is stored in the command register from the outside after the split response is made and an execution is instructed, the debugging circuit sends a signal indicating that command transfer preparation has been completed.

5. The integrated circuit according to claim 1 , wherein, when a signal indicating that the command transfer preparation has been completed is sent from the debugging circuit, the processing unit acquires the use right of the bus and reads the command from the debugging circuit via the bus.

6. A debugging circuit that is coupled to a processing unit that executes a user program via a bus, the debugging circuit comprising:

a command register configured to store a command; and

a control circuit configured to transfer the command to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit executes a command including a break factor in the user program, the processing unit halts the execution of the user program and makes the command transfer request to the control circuit,

the control circuit makes a split response for freeing a use right of the bus from the processing unit in a period between the command transfer request and a command transfer operation,

the processing unit frees the use right of the bus and enters a wait state,

the control circuit prepares a debugging command in the command register and transfers the debugging command to the processing unit via the bus, and

the processing unit restarts the execution of the halted user program after executing the debugging command,

wherein the debugging circuit is settable in one of a first operation mode in which the split response is made and a second operation mode in which the split response is not made,

in an initial state, a command for branching to a specific address is stored in the command register of the debugging circuit, and

when the debugging circuit is set in the second operation mode, the debugging circuit immediately transfers the command for branching to the specific address to the processing unit in response to the command transfer request,

wherein after the processing unit executes the command for branching to the specific address and a command that begins from the specific address, and issues a subsequent command transfer request to the debugging circuit, the debugging circuit makes the split response even when the debugging circuit is set in the second operation mode.

7. The debugging circuit according to claim 6 , wherein

the control circuit has a function of accessing a memory via the bus in response to external control.

8. The debugging circuit according to claim 6 , wherein

the split response includes a response to the processing unit indicating being in preparation for a response.

9. The debugging circuit according to claim 6 , wherein,

when a desired command is stored in the command register from the outside after the split response is made, and an execution is instructed, the control circuit sends a signal indicating that command transfer preparation has been completed.

10. A debugging command control method for use with an integrated circuit, comprising:

a bus,

a processing unit configured to execute a user program, and

a debugging circuit coupled to the bus, the debugging circuit transferring a command to the processing unit via the bus in response to a command transfer request from the processing unit,

the debugging command control method comprising:

halting the execution of the user program and transmitting the command transfer request from the processing unit to the debugging circuit;

sending, in response to the command transfer request, a split response from the debugging circuit to the processing unit for freeing a use right of the bus from the processing unit;

freeing the use right of the bus from the processing unit in response to the split response;

preparing a debugging command in the command register and transferring the debugging command to the processing unit via the bus;

executing the halted user program after executing the debugging command;

configuring the debugging circuit in one of a first operation mode in which the split response is made and a second operation mode in which the split response is not made;

in an initial state, storing a command for branching to a specific address in the command register of the debugging circuit;

when the debugging circuit is set in the second operation mode, configuring the debugging circuit to immediately transfer the command for branching to the specific address to the processing unit in response to the command transfer request; and

after the processing unit executes the command for branching to the specific address and a command that begins from the specific address, and issues a subsequent command transfer request to the debugging circuit, configuring the debugging circuit to make the split response even when the debugging circuit is set in the second operation mode.

11. The debugging command control method according to claim 10 , further comprising:

sending, from the debugging circuit, a signal indicating that command transfer preparation has been completed; and

acquiring, by the processing unit, the use right of the bus when the signal indicating that the command transfer preparation is completed is sent, and reading a command from the debugging circuit via the bus.