FBM generation device and FBM generation method
A fail bit map generation device quickly generating an FBM identifies an abnormal address from a first mismatch detection cycle number obtained in a shipment test and shipment sequence information used in the shipment test. The fail bit map generation device generates a bit identifying pattern that does not perform reading and writing at an address determined as being normal in the shipment test to compensate for read data information that is insufficient for generating the FBM. The fail bit map generation device identifies an abnormal bit from a second mismatch detection cycle number obtained by a tester with the bit identifying pattern and generates the FBM from the abnormal bit and the abnormal address.
1 . A fail bit map generation device generating a fail bit map for a semiconductor memory device embedded in a semiconductor integrated circuit device, the fail bit map generation device generating the fail bit map in cooperation with a tester testing the semiconductor integrated circuit device and a built-in self-test circuit, embedded in the semiconductor integrated circuit device, diagnosing the semiconductor memory device, wherein the built-in self-test circuit sets a mismatch detection flag to ON when an output of the semiconductor memory device and an expected value generated by the built-in self-test circuit are mismatched during a period in which the tester is conducting a shipment test on the semiconductor integrated circuit device, the fail bit map generation device comprising:
an abnormal address identifying unit identifying an abnormal address from a first mismatch detection cycle number when the mismatch detection flag is set to ON and shipment test sequence information, which is a sequence of the shipment test;
a bit identifying pattern generation unit generating a bit identifying pattern, the bit identifying pattern being a pattern of m+1 cycles in which reading is started from a state of the built-in self-test circuit corresponding to m cycles before when the mismatch detection flag is set to ON and operation of the built-in self-test circuit is ended when the mismatch detection flag is set to ON; and
a fail bit map generation unit identifying an abnormal bit from a second mismatch detection cycle number indicating that the output of the semiconductor memory device, which is obtained when the tester tests the semiconductor memory device with the bit identifying pattern, and an expected value in the bit identifying pattern do not match and generating the fail bit map from the identified abnormal bit and the abnormal address.
2 . The fail bit map generation device according to claim 1 , wherein m of the m+1 cycles of the bit identifying pattern is greater than or equal to one.
3 . The fail bit map generation device according to claim 1 , wherein m of the m+1 cycles of the bit identifying pattern is zero.
4 . The fail bit map generation device according to claim 1 , wherein:
the abnormal address identifying unit reads the first mismatch detection cycle number stored in a memory device; and
the fail bit map generation unit reads the second mismatch detection cycle number stored in the memory device.
5 . A method for generating a fail bit map for a semiconductor memory device embedded in a semiconductor integrated circuit device, the method generating the fail bit map in cooperation with a tester testing the semiconductor integrated circuit device and a built-in self test circuit, embedded in the semiconductor integrated circuit device, diagnosing the semiconductor memory device, wherein the built-in self-test circuit sets a mismatch detection flag to ON when an output of the semiconductor memory device and an expected value generated by the built-in self-test circuit are mismatched during a period in which the tester is conducting a shipment test on the semiconductor integrated circuit device, the method comprising:
specifying an abnormal address from a first mismatch detection cycle number when the mismatch detection flag is set to ON and shipment test sequence information, which is a sequence of the shipment test;
generating a bit identifying pattern, the bit identifying pattern being a pattern of m+1 cycles in which reading is started from a state of the built-in self-test circuit corresponding to m cycles before when the mismatch detection flag is set to ON and operation of the built-in self-test circuit is ended when the mismatch detection flag is set to ON; and
specifying an abnormal bit from a second mismatch detection cycle number indicating that the output of the semiconductor memory device, which is obtained when the tester tests the semiconductor memory device with the bit identifying pattern, and an expected value in the bit identifying pattern do not match and generating the fail bit map from the identified abnormal bit and the abnormal address.
6 . The method according to claim 5 , wherein m of the m+1 cycles of the bit identifying pattern is greater than or equal to one.
7 . The method according to claim 5 , wherein m of the m+1 cycles of the bit identifying pattern is zero.