Wafer structure with a plurality of functional macro chips for chip-on-chip configuration
View Patent ↗A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.
1. A semiconductor device comprising:
a plurality of functional macro chips separable from the semiconductor device, each including a macro region, wherein the macro regions are arranged adjacent to each other; and
a pad region for the functional macro chips surrounding the macro regions.
2. The semiconductor device according to claim 1 , further comprising:
a plurality of input/output signal wires for connecting the macro regions and the pad region.
3. The semiconductor device according to claim 1 , further comprising:
a plurality of signal wires and a plurality of output signal lines connecting the macro regions and the pad region.
4. The semiconductor device according to claim 1 , wherein the macro regions and the pad region are formed on a single wafer.
5. A semiconductor device having a chip-on-chip configuration, the semiconductor device comprising
a first chip; and
a second chip including a macro region and mounted on the first chip, wherein the second chip is substantially identical in size with the macro region;
wherein the second chip is one of a plurality of functional macro chips formed in a wafer, the functional macro chips being separable from the wafer and arranged adjacent to each other, the wafer including the functional macro chips and a pad region, the pad region surrounding the functional macro chips.
6. A method for forming a plurality of functional macro chips from a wafer, the method comprising:
forming the functional macro chips, with each including a macro region, in the wafer, with the macro chips arranged adjacent to each other; wherein the functional macro chips are separable from the wafer; and
forming a pad region in the wafer, with the pad region being shared by the functional macro chips and surrounding the functional macro chips.
7. The method according to claim 6 , further comprising:
cutting the functional macro chips apart from the wafer so that the functional macro chips are each substantially identical in size to the corresponding macro region.
8. The semiconductor device according to claim 1 , wherein each of the plurality of functional macro chips is substantially identical in size to the corresponding macro region.
9. The method according to claim 6 , wherein each of the plurality of functional macro chips is substantially identical in size to the corresponding macro region.