Data transfer control apparatus and data transfer control method

1. A data transfer control apparatus comprising:

a memory;

a write control part controlling data writing to the memory;

a read control part controlling data reading from the memory;

a read-start calculation part calculating an output timing of a notification which indicates a read-start operation to start the data reading to the read control part based on each transfer condition of the data writing to the memory and the data reading from the memory; and

an asynchronous transfer part outputting the notification to the read control part, wherein the read-start calculation part includes a comparator to compare a number of one time transfer cycles counted by a counter and a value calculated based on a total transfer size notified from the write control part and to output the notification based on a comparison result,

wherein the value is obtained by selecting a shifter from a plurality of shifters based on a selection signal and shifting binary data corresponding to the total transfer size by a selected shifter.

2. The data transfer control apparatus according to claim 1 , wherein

the counter counts the number of one time transfer cycles based on a length of a strobe signal output from a memory control part, and

the comparator outputs the notification at the timing when the comparison result indicates matching.

3. The data transfer control apparatus according to claim 2 , wherein

the read-start calculation part includes,

a conversion part calculates the value from the total transfer size notified from the write control part based on an operating frequency and a coefficient indicating a number of bits transferred per cycle in a processing apparatus side and a second memory which is different from the memory.

4. The data transfer control apparatus according to claim 3 , wherein data transfer interruption cycles are included in the second memory as the coefficient.

5. The data transfer control apparatus according to claim 3 , wherein the coefficient is preset in an external register based on transfer conditions of the processing apparatus side and the second memory.

6. The data transfer control apparatus according to claim 1 , wherein a second value to be input to the comparator as the value is obtained by adding a data transfer interruption cycle to the value by an adder.

7. A data transfer control method comprising:

calculating an output timing of a notification which indicates the start of a reading from a memory based on each transfer condition of a writing to the memory in a second memory which is different from the memory and a reading from the memory in a processing apparatus side;

obtaining the value by selecting a shifter from a plurality of shifters based on a selection signal and shifting binary data corresponding to a total transfer size by a selected shifter;

comparing a number of one time transfer cycles counted by a counter and the value;

outputting the notification based on a comparison result; and

notifying the notification.

8. The data transfer control method according to claim 7 , wherein

the number of one time transfer cycles is counted based on a length of a strobe signal from a memory control part; and

the notification is output at the timing when the comparison result indicates matching.

9. The data transfer control method according to claim 8 , further comprising,

calculating the value from a total transfer size based on an operating frequency and a coefficient indicating a number of bits transferred per cycle in the processing apparatus side and the second memory.

10. The data transfer control method according to claim 9 , wherein

the coefficient comprises data transfer interruption cycles in the memory.