Critical path estimating program, estimating apparatus, estimating method, and integrated circuit designing program
View Patent ↗A computer-readable recording medium on which is recorded a program, which is used by a computer for estimating a critical path among a plurality of paths given as paths within an integrated circuit, for causing the computer to execute a process, the process comprising receiving from a memory inputs of a logic description for the integrated circuit, and the plurality of given paths, obtaining a path evaluation value, which represents a delay of a path, for each of the given paths, and prioritizing the paths according to evaluation values, and estimating a path having a large evaluation value as the critical path.
1. A computer-readable recording medium on which is recorded a program, which is used by a computer for estimating a critical path among a plurality of paths given as paths within an integrated circuit, for causing the computer to execute a process, the process comprising:
receiving from a memory inputs of a logic description for the integrated circuit, and the plurality of given paths;
obtaining a path evaluation value, which represents a delay of a path, for each of the given paths; and
prioritizing the paths according to evaluation values, and estimating a path having a large evaluation value as the critical path;
wherein the plurality of given paths are paths extracted as exception paths.
2. The computer-readable recording medium according to claim 1 , wherein
in said obtaining the path evaluation value,
the evaluation value is obtained by using a number of stages of basic gates within a path, and a wire for a logic module configured by a plurality of basic gates arranged in a short distance range within the integrated circuit as delay factors of the path.
3. The computer-readable recording medium according to claim 2 , wherein
in said obtaining the path evaluation value,
the evaluation value is obtained by using a wire for a physical layer, which is passed by the path, as a scale for which an automatic layout design is made with a process once executed, as a further delay factor of the path.
4. The computer-readable recording medium according to claim 3 , wherein
in said obtaining the path evaluation value,
the evaluation value is obtained by using a space of the physical layer, which is passed by the path, as a further delay factor of the path.
5. The computer-readable recording medium according to claim 2 , wherein
in said obtaining the path evaluation value,
the evaluation value is obtained by using a number of fan-outs of a gate included in the path as a further delay factor of the path.
6. The computer-readable recording medium according to claim 2 , wherein
in said obtaining the path evaluation value,
the evaluation value is obtained by using a position of a gate of a fan-out destination included in the path as a further delay factor of the path.
7. The computer-readable recording medium according to claim 2 , wherein
in said obtaining the path evaluation value,
the evaluation value is obtained by using a space of the logic module including the path as a further delay factor of the path.
8. The computer-readable recording medium according to claim 2 , wherein
in said obtaining the path evaluation value,
the evaluation value is obtained by using a frequency of a clock signal corresponding to the path as a further delay factor of the path.
9. The computer-readable recording medium according to claim 1 , the process further comprising:
handling a path, which is estimated as the critical path, among the extracted exception paths as an exception path, and making a layout of the integrated circuit.
10. An apparatus for estimating a critical path among a plurality of paths given as paths within an integrated circuit, comprising:
an inputting unit for receiving from a memory inputs of a logic description for the integrated circuit, and the plurality of given paths;
an evaluation value calculating unit for obtaining a path evaluation value, which represents a delay of a path, for each of the plurality of given paths; and
a prioritizing/processing unit for prioritizing the paths according to evaluation values, and for estimating a path having a large evaluation value as the critical paths;
wherein the plurality of given paths are paths extracted as exception paths.
11. A method for estimating a critical path among a plurality of paths given as paths within an integrated circuit, comprising:
receiving from a memory inputs of a logic description for the integrated circuit, and the plurality of given paths;
obtaining a path evaluation value, which represents a delay of a path, for each of the given paths; and
prioritizing the paths according to evaluation values, and estimating a path having a large evaluation value as the critical path;
wherein the plurality of given paths are paths extracted as exception paths.