Timing analyzing method and apparatus for semiconductor integrated circuit

1. A method for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a best-case corner condition and a worst-case corner condition, wherein the best-case corner condition and the worst-case corner condition each include a temperature condition, with each temperature condition being one of a high temperature condition and a low temperature condition, the method comprising:

storing in a temperature characteristic coefficient table a temperature characteristic coefficient for each of temperature-reversed corner conditions that are generated by selectively reversing the temperature conditions of the best-case corner condition and the worst-case corner condition; and

performing timing analysis under said temperature-reversed corner conditions based on a gate delay and net delay, which are calculated under the best-case corner condition and the worst-case corner condition, and the temperature characteristic coefficient.

2. The method according to claim 1 , further comprising:

performing layout correction satisfying hold margin and slack time under each of the corner conditions after performing the timing analysis under said temperature-reversed corner conditions.

3. The method according to claim 2 , wherein said performing layout correction includes inserting a buffer circuit at a section having a large net delay.

4. The method according to claim 2 , wherein said performing layout correction includes replacing a buffer circuit in a section having a large net delay with a buffer circuit having a high load drive capacity.

5. The method according to claim 2 , wherein said performing layout correction includes replacing two stages of buffer circuits with an inverter circuit.

6. A method for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a first corner condition, which is a combination of a high temperature condition, a low voltage condition, and a slow process condition, and a second corner condition, which is a combination of a low temperature condition, a high temperature condition, and a fast process condition, the method comprising:

selectively reversing the temperature condition of the first corner condition to generate a fourth corner condition, which is a combination of the low temperature condition, the low voltage condition, and the slow process condition;

selectively reversing the temperature condition of the second corner condition to generate a third corner condition, which is a combination of the high temperature condition, the high voltage condition, and the fast process condition;

storing a temperature characteristic coefficient for the fourth corner condition and a temperature characteristic coefficient for the third corner condition in a temperature characteristic coefficient table;

performing timing analysis under the first corner condition and the second corner condition to calculate a gate delay and net delay under the first corner condition and a gate delay and net delay under the second corner condition; and

performing timing analysis under the third corner condition and the fourth corner condition based on the gate delay and net delay in the first corner condition, the gate delay and net delay in the second corner condition, and the temperature characteristic coefficients stored in the temperature characteristic coefficient table.

7. The method according to claim 6 , further comprising:

calculating the temperature characteristic coefficient from a ratio between a temperature characteristic of the first and second corner conditions and a temperature characteristic of the third and fourth corner conditions, and storing the temperature characteristic coefficient in the temperature characteristic coefficient table.

8. The method according to claim 6 , further comprising:

performing layout correction satisfying hold margin and slack time under each of the corner conditions after performing the timing analysis under the third corner condition and the fourth corner condition.

9. The method according to claim 8 , wherein said performing layout correction includes inserting a buffer circuit at a section having a large net delay.

10. The method according to claim 8 , wherein said performing layout correction includes replacing a buffer circuit in a section having a large net delay with a buffer circuit having a high load drive capacity.

11. The method according to claim 8 , wherein said performing layout correction includes replacing two stages of buffer circuits with an inverter circuit.

12. The method according to claim 6 , wherein timing analysis is performed under the first to fourth corner conditions but not under other corner conditions.

13. An apparatus for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a best-case corner condition and a worst-case corner condition, wherein the best-case corner condition and the worst-case corner condition each include a temperature condition, with each temperature condition being a high temperature condition or a low temperature condition, the apparatus comprising:

a timing list storing a delay characteristic of cells and conductive paths in the semiconductor integrated circuit;

a slack file storing slack time of the cell;

a temperature characteristic coefficient table storing a temperature characteristic coefficient for each of temperature-reversed corner conditions generated by selectively reversing the temperature conditions of the best-case corner condition and the worst-case corner condition; and

an automatic timing engineering change device for performing timing analysis under said temperature-reversed corner conditions based on a gate delay and net delay, which are calculated under the best-case corner condition and the worst-case corner condition, and the temperature characteristic coefficient.