Communication test circuit, communication interface circuit, and communication test method

1. A communication test circuit for testing a communication interface circuit which restores a clock signal from a received signal and detects data, the communication test circuit comprising:

an adder that receives a phase adjustment signal for adjusting a data detection timing at which the data is detected from the received signal, in accordance with a phase of the received signal, and a prescribed offset, and calculates an offset phase adjustment signal by adding the offset to the phase adjustment signal; and

a clock generation block that receives the offset phase adjustment signal calculated by the adder and outputs the clock signal adjusted in accordance with the offset phase adjustment signal,

wherein the adder receives the offset as a test code that can be variably specified from an outside and specifies an offset value to be added to the phase adjustment signal in accordance with the test code.

2. The communication test circuit according to claim 1 , further comprising a selector that outputs the offset when test information indicates that a test is in progress, and outputs zero as the offset when the test information indicates that no test is in progress.

3. A communication test circuit for testing a communication interface circuit which restores a first clock signal and a second clock signal from a received signal and detects data, the communication test circuit comprising:

an adder that receives a prescribed offset and a phase adjustment signal specifying phase adjustment in accordance with the received signal, with respect to the first clock signal determining either one timing of a boundary detection timing for detecting a transition point of the data from the received signal and a data detection timing for detecting the data from the received signal, and the second clock signal determining another timing, and calculates an offset phase adjustment signal by adding the offset to the phase adjustment signal;

a first clock generation block that receives the phase adjustment signal directly and outputs the first clock signal, a phase of which is adjusted in accordance with the phase adjustment signal; and

a second clock generation block that receives the offset phase adjustment signal with the offset added by the adder and outputs the second clock signal, a phase of which is adjusted in accordance with the offset phase adjustment signal.

4. The communication test circuit according to claim 3 , wherein the adder receives the offset as a test code which can be variably specified from an outside and specifies an offset value to be added to the phase adjustment signal in accordance with the test code.

5. The communication test circuit according to claim 3 , further comprising a selector that outputs the offset when test information indicates that a test is in progress, and outputs zero as the offset when the test information indicates that no test is in progress.

6. A communication interface circuit for restoring a first clock signal and a second clock signal from a received signal and detecting data, the communication interface circuit comprising:

a phase adjustment signal generation block that generates, in accordance with the received signal, a phase adjustment signal for adjusting, in accordance with variations in phase of the received signal, the first clock signal determining either one timing of a boundary detection timing for detecting a transition point of the data from the received signal and a data detection timing for detecting the data from the received signal, and the second clock signal determining another timing;

an adder that receives the phase adjustment signal and a prescribed offset and calculates an offset phase adjustment signal by adding the offset to the phase adjustment signal;

a first clock generation block that receives the phase adjustment signal directly and outputs the first clock signal, a phase of which is adjusted in accordance with the phase adjustment signal;

a second clock generation block that receives the offset phase adjustment signal with the offset added by the adder, and outputs the second clock signal, a phase of which is adjusted in accordance with the offset phase adjustment signal; and

a data detection block that detects the data from the received signal in accordance with the data detection timing determined by one of the second clock signal and the first clock signal.

7. A communication test method for testing a communication interface circuit which restores a first clock signal and a second clock signal from a received signal and detects data, the communication test method comprising:

receiving a phase adjustment signal for specifying phase adjustment in accordance with the received signal, with respect to the first clock signal determining either one timing of a boundary detection timing for detecting a transition point of the data from the received signal and a data detection timing for detecting the data from the received signal, and the second clock signal determining another timing, also receiving a prescribed offset at a test;

calculating an offset phase adjustment signal by adding the offset to the phase adjustment signal;

adjusting a phase of the first clock signal in accordance with the phase adjustment signal;

adjusting a phase of the second clock signal in accordance with the offset phase adjustment signal; and

shifting either one of the data detection timing and the boundary detection timing from the timing determined by the received signal.