IP Library Patent Application 12005616
Patent Application
App. No. 12/005,616

Method of designing semiconductor integrated circuit, design device, and CAD program

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Quick Facts
Patent No.
US None
App. No.
12/005,616
Abstract

A semiconductor integrated circuit design device capable of carrying out design by evaluating a crosstalk between blocks has been disclosed. The integrated circuit design device is adapted to design a semiconductor integrated circuit having a plurality of blocks and comprises a virtual noise source setting PORTION that sets a virtual noise source at a neighboring boundary with a neighboring block of each block, a block design PORTION that carries out design of each block while taking into consideration influence from the virtual noise source, and an assembly design PORTION that assembles the plurality of the designed hierarchical blocks.

Claims (24)

1 . A method of designing a semiconductor integrated circuit by designing each of a plurality of the blocks of a semiconductor integrated circuit having the plurality of blocks and assembling the plurality of the designed blocks,

wherein a virtual noise source is set at a neighboring boundary with a neighboring block of each block, and

design of each block is carried out while taking into consideration the influence from the virtual noise source of the neighboring block.

2 . The method of designing a semiconductor integrated circuit as set forth in claim 1 ,

wherein the position and noise strength of the virtual noise source is set in advance by a designer.

3 . The method of designing a semiconductor integrated circuit as set forth in claim 1 ,

wherein a wire crosstalk due to the virtual noise source of the neighboring block is analyzed in each block and design of each block is carried out while taking the result of analysis into consideration.

4 . The method of designing a semiconductor integrated circuit as set forth in claim 3 ,

wherein design data is changed in accordance with the result of analysis of the wire crosstalk in each of the blocks to prevent a crosstalk error from occurring.

5 . An integrated circuit design device for designing a semiconductor integrated circuit having a plurality of blocks, comprising:

a virtual noise source setting portion that sets a virtual noise source at a neighboring boundary with a neighboring block of each block;

a block design portion that carries out design of each block while taking into consideration the influence from the virtual noise source; and

an assembly design portion for assembling the plurality of designed hierarchical blocks.

6 . The semiconductor integrated circuit design device as set forth in claim 5 ,

wherein the virtual noise source setting portion sets the position and noise strength of the virtual noise resource based on an input from the outside.

7 . The semiconductor integrated circuit design device as set forth in claim 5 , further comprising a crosstalk analysis portion that analyzes a wire crosstalk resulting from the virtual noise resource in a neighboring block in each block,

wherein design of each block is carried out while taking the result of analysis into consideration.

8 . A CAD program for causing a computer to operate to design a semiconductor integrated circuit by designing each of a plurality of blocks of a semiconductor integrated circuit having the plurality of blocks and then assembling the plurality of the designed blocks, the CAD program causing a computer to operate to:

set a virtual noise resource at a neighboring boundary with a neighboring block of each block; and

design each block while taking into consideration the influence from the virtual noise source of the neighboring block.

9 . The CAD program as set forth in claim 8 ,

wherein the CAD program causes a computer to set the position and noise strength of the virtual noise source input from the outside.

10 . The CAD program as set forth in claim 8 ,

wherein the CAD program causes a computer to analyze a wire crosstalk resulting from the virtual noise source of the neighboring block in each block and to design each block while taking the result of analysis into consideration.

Assignments (3)
CHANGE OF NAME Recorded Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2007
From: NAKAMORI, TSUTOMU
To: FUJITSU LIMITED
Reel/Frame 020348/0744 →