Patent Assignment
Reel/Frame 012856/0780
Assignment of Assignor's Interest
Recorded: 2002-05-01
Received: 2002-05-08
Pages: 3
Assignor
KATAYOSE, YUUJI
Executed: 2002-04-23
Assignee
NEC CORPORATION
MINATO-KU, 7-1, SHIBA 5-CHOME, TOKYO, JPX, JAPAN
Covered Property
(1)
Method of Designing Integrated Circuit Using Hierarchical Design Technique
Application:
10/136,414 →