Granted Patent
Utility
US 6,718,531
· Confirmation No. 7634
METHOD OF DESIGNING INTEGRATED CIRCUIT USING HIERARCHICAL DESIGN TECHNIQUE
Inventor:
Yuuji Katayose
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2004-02-17 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2002-05-01 | TRNA |
Transmittal of New Application | 1 | View | |
| 2002-05-01 | SPEC |
Specification | 34 | View | |
| 2002-05-01 | CLM |
Claims | 11 | View | |
| 2002-05-01 | ABST |
Abstract | 1 | View | |
| 2002-05-01 | DRW |
Drawings-only black and white line drawings | 12 | View | |
| 2002-05-01 | OATH |
Oath or Declaration filed | 4 | View |
Inventors
Yuuji Katayose
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
716/10
G06F30/39
Prosecution
- Examiner
- LEVIN, NAUM B
- Art Unit
- 2825
- Customer No.
- 27667
- Docket No.
- NEC 02USFP755
- Confirmation No.
- 7634
Foreign Priority
140774/2001
·
2001-05-10
·
JAPAN
Publication
- Pub. No.
- US20020170026A1
- Pub. Date
- 2002-11-14
Patent Term Adjustment
0days
No related applications found.
CHANGE OF ADDRESS
Recorded 2017-11-29
from
NEC CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-02-19
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Quick Facts
- Patent No.
- US 6,718,531
- App. No.
- 10/136,414
- Filed
- 2002-05-01
- Granted
- 2004-04-06
- Pub. No.
- US20020170026A1
- Examiner
- LEVIN, NAUM B
- Art Unit
- 2825
- PTA
- 0 days
External Links