Patent Assignment
Reel/Frame 012888/0510
Assignment of Assignor's Interest
Recorded: 2002-05-09
Pages: 3
Assignor
ITO, YOSHIAKI
Executed: 2002-04-24
Assignee
MITSUBISHI DENKI KABUSHIKI KAISHA
2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 100-8310, JAPAN
Covered Property
(1)
Pll Circuit Including a Control Logic Circuit for Adjusting the Delay Times of the Clocks So That the Phase Error of the Clocks Is Reduced
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.