IP Library › Assignment 013017/0219
Patent Assignment
Reel/Frame 013017/0219

Assignment of Assignor's Interest

Recorded: 2002-06-14 Pages: 3
Assignor
WONG, SAU CHING
Executed: 2002-06-14
Assignee
MULTI LEVEL MEMORY TECHNOLOGY
SUITE 115, 960 SARATOGA AVENUE,, SAN JOSE, CALIFORNIA, 95129
Covered Property (1)
Bit Line Reference Circuits for Binary and Multiple-Bit-Per-Cell Memories
Patent: 6,906,951 →
Application: 10/173,468 →
Publication: US 2003/0043621
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 28, 2005
From: MULTI LEVEL MEMORY TECHNOLOGY (CALIFORNIA)
To: MULTI LEVEL MEMORY TECHNOLOGY (NEVADA)
Reel/Frame 016800/0640 →
Assignment of Assignor's Interest Aug 24, 2005
From: MULTI LEVEL MEMORY TECHNOLOGY
To: INTERNATIONAL DEVELOPMENT AND LICENSING
Reel/Frame 017176/0517 →
Assignment of Assignor's Interest Feb 3, 2006
From: INTERNATIONAL DEVELOPMENT AND LICENSING
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 017230/0319 →