Patent Assignment
Reel/Frame 013612/0449
Assignment of Assignor's Interest
Recorded: 2002-12-23
Received: 2003-01-02
Pages: 2
Assignor
MIYAMOTO, TETSUO
Executed: 2002-10-26
Assignee
FUJITSU LIMITED
1-1 KAMIKODANAKA, 4-CHOME, NAKAHARA-KU,, KAWASAKI-SHI, KANAGAWA 211-8588, JPX, JAPAN
Covered Property
(1)
Integrated Circuit Layout Method and Program for Mitigating Effect Due to Voltage Drop of Power Supply Wiring
Application:
10/325,964 →