IP Library › Patent Application 10325964
Patent Application Utility
App. No. 10/325,964 · Confirmation No. 5017

INTEGRATED CIRCUIT LAYOUT METHOD AND PROGRAM FOR MITIGATING EFFECT DUE TO VOLTAGE DROP OF POWER SUPPLY WIRING

Inventor: Tetsuo Miyamoto
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362 View Patent ↗ View Publication ↗
⬇ PDF
 Code Description Pages PDF
2004-08-13 IFEE Issue Fee Payment (PTO-85B) 1 View
2004-06-03 NOA Notice of Allowance and Fees Due (PTOL-85) 3 View
2004-06-03 NOA Notice of Allowance and Fees Due (PTOL-85) 4 View
2004-06-03 1449 List of References cited by applicant and considered by examiner 1 View
2004-06-03 892 List of references cited by examiner 1 View
2004-06-03 IIFW Issue Information including classification, examiner, name, claim, renumbering, etc. 1 View
2004-06-03 FWCLM Index of Claims 1 View
2004-06-03 SRFW Search information including classification, databases and other search related notes 1 View
2004-05-21 SRNT Examiner's search strategy and results 16 View
2002-12-23 TRNA Transmittal of New Application 2 View
2002-12-23 SPEC Specification 20 View
2002-12-23 CLM Claims 4 View
2002-12-23 ABST Abstract 1 View
2002-12-23 DRW Drawings-only black and white line drawings 13 View
2002-12-23 OATH Oath or Declaration filed 3 View
2002-12-23 WFEE Fee Worksheet (SB06) 1 View
2002-12-23 WFEE Fee Worksheet (SB06) 1 View
2002-12-23 IDS Information Disclosure Statement (IDS) Form (SB08) 3 View
2002-12-23 FOR Foreign Reference 7 View
2002-12-23 FOR Foreign Reference 7 View
2002-12-23 FOR Foreign Reference 19 View
2002-12-23 FRPR Certified Copy of Foreign Priority Application 40 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
App. No.
10/325,964
Filed
2002-12-23
Granted
2004-09-28
Pub. No.
US20030177461A1
Examiner
LIN, SUN J
Art Unit
2825
PTA
0 days