IP Library › Assignment 013927/0559
Patent Assignment
Reel/Frame 013927/0559

Assignment of Assignor's Interest

Recorded: 2003-03-31 Pages: 3
Assignors
LEE, JIUNN
Executed: 2003-03-17
JEN, CHIN-PIN
Executed: 2003-03-17
YANG, MING-CHANG
Executed: 2003-03-17
CHEN, HUNG-CHIEH
Executed: 2003-03-17
Assignee
SILICON INTEGRATED SYSTEMS, CORP.
NO. 16, CREATION RD. 1, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, R.O.C., TAIWAN
Covered Property (1)
Methodology of Locating Faults of Scan Chains in Logic Integrated Circuits
Patent: 7,076,707 →
Application: 10/401,701 →
Publication: US 2004/0181722
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 27, 2005
From: SILICON INTEGRATED SYSTEMS CORP.
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 015621/0932 →