Patent Assignment
Reel/Frame 015621/0932
Assignment of Assignor's Interest
Recorded: 2005-01-27
Pages: 3
Assignor
SILICON INTEGRATED SYSTEMS CORP.
Executed: 2005-01-26
Assignee
UNITED MICROELECTRONICS CORP.
NO. 3, LI-HSIN RD. II, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, R.O.C., TAIWAN
Covered Properties
(39)
Fixing Device for Setting Anti-Shock Foot Stand
Patent:
6,409,129 →
Application:
09/654,228 →
Dual Damascene Process Using an Oxide Liner for a Dielectric Barrier Layer
Method of Rapid Prevention of Particle Pollution in Pre-Clean Chambers
Method of Prevention of Particle Pollution in a Pre-Clean Chamber
Method for Forming a Dual Damascene Structure Having Capacitors
Patent:
6,391,713 →
Application:
09/854,872 →
Method for Measuring Width of Bottom Under Cut During Etching Process
Method for forming metal capacitors with a damascene process
Patent:
6,338,999 →
Application:
09/880,782 →
Method for Forming a Metal Capacitor in a Damascene Process
Method for fabricating metal capacitor
Patent:
6,358,792 →
Application:
09/881,101 →
Method for Forming a Metal Capacitor in a Damascene Process
Patent:
6,410,386 →
Application:
09/881,102 →
Method for Forming Selective Protection Layers on Copper Interconnects
Dual Damascene Process Using Metal Hard Mask
Organic Copper Diffusion Barrier Layer
Patent:
6,503,835 →
Application:
09/939,606 →
Apparatus and Method for Cleaning Wafers with Contact Holes or via Holes
Scrubbing Assembly for Wafer-Cleaning Device
Method for Removing the Circumferential Edge of a Dielectric Layer
Metal Capacitors with Damascene Structures and Method for Forming the Same
Metal Capacitors with Damascene Structures
Process for Device Isolation
Patent:
6,489,193 →
Application:
10/040,442 →
Method of Reducing Micro-Scratches During Tungsten Cmp
Patent:
6,548,409 →
Application:
10/076,395 →
Method of Forming a Stacked Dielectric Layer on a Semiconductor Substrate Having Metal Patterns
Patent:
6,593,225 →
Application:
10/087,773 →
Capacitor with Lower Electrode Located at the Same Level as an Interconnect Line
Method for Fabricating Polysilicon Capacitor
Method for Manufacturing a Mos Device with Improved Well Control Stability
Patent:
6,509,238 →
Application:
10/100,676 →
Metal Capacitor in Damascene Structures
Dual Damascene Structure Having Capacitors
Method of Forming Salicide
Method for Improving Adhesion of a Low K Dielectric to a Barrier Layer
Dual Damascene Process
Patent:
6,495,448 →
Application:
10/165,794 →
Storage and management method for a multi-floor stocker system
Application:
10/230,062 →
Publication:
US 2004/0054543
Method of Forming a Metal-Oxide Semiconductor Transistor
Method of Forming Shallow Trench Isolation in a Semiconductor Substrate
Method of Forming Shallow Trench Isolation in a Semiconductor Substrate
Method of Forming a Shallow Trench Isolation Structure
Method of etching a low-k dielectric layer
Application:
10/321,565 →
Publication:
US 2004/0121604
Method of etching a metal line
Application:
10/372,842 →
Publication:
US 2004/0166691
Methodology of Locating Faults of Scan Chains in Logic Integrated Circuits
Method of Fabricating Stacked Gate Dielectric Layer
Application:
10/446,871 →
Publication:
US 2004/0241948
Method of Improving Surface Planarity
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 28, 2001
From: LEE, SHYH-DAR
To: SILICON INTEGRATED SYSTEMS CORP.
Reel/Frame 012129/0110 →
Assignment of Assignor's Interest
Sep 5, 2001
From: TSAI, LUNG HUI; HUANG, YU-LING; CHANG, HSIN YI
To: SILICON INTEGRATED SYSTEMS CORP.
Reel/Frame 012160/0191 →
Assignment of Assignor's Interest
Oct 11, 2001
From: TSENG, KAO-MAO; TSENG, SU-LING; CHANG, HSIN YI
To: SILICON INTEGRATED SYSTEMS CORP.
Reel/Frame 012249/0301 →
Assignment of Assignor's Interest
Nov 5, 2001
From: HUANG, YU-LING; TSAI, LUNG HUI
To: SILICON INTEGRATED SYSTEMS CORPS.
Reel/Frame 012296/0796 →
Assignment of Assignor's Interest
Dec 21, 2001
From: HSUE, CHEN-CHIU; LEE, SHYH-DAR
To: SILICON INTEGRATED SYSTEMS CORPORATION
Reel/Frame 012401/0275 →
Assignment of Assignor's Interest
Dec 21, 2001
From: HSUE, CHEN-CHIU; LEE, SHYH-DAR
To: SILICON INTEGRATED SYSTEMS CORPORATION
Reel/Frame 012401/0331 →
Assignment of Assignor's Interest
Jan 9, 2002
From: CHEN, LUNG; WANG, TENG-FENG; YANG, ZEN-LONG; CHANG, SHIH-HUI
To: SILICON INTEGRATED SYSTEMS CORP.
Reel/Frame 012464/0805 →
Assignment of Assignor's Interest
Jul 18, 2011
From: UNITED MICROELECTRONICS CORP.
To: INTELLECTUAL VENTURES FUND 74 LLC
Reel/Frame 026605/0333 →
Assignment of Assignor's Interest
Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
Assignment of Assignor's Interest
Feb 12, 2023
From: INTELLECTUAL VENTURES HOLDING 81 LLC
To: INTELLECTUAL VENTURES ASSETS 186 LLC
Reel/Frame 062667/0369 →
Security Interest
Mar 24, 2023
From: MIND FUSION, LLC
To: INTELLECTUAL VENTURES ASSETS 191 LLC; INTELLECTUAL VENTURES ASSETS 186 LLC
Reel/Frame 063295/0001 →
Assignment of Assignor's Interest
Jul 13, 2023
From: INTELLECTUAL VENTURES ASSETS 186 LLC
To: MIND FUSION, LLC
Reel/Frame 064271/0001 →