Patent Assignment
Reel/Frame 014393/0769
Assignment of Assignor's Interest
Recorded: 2004-03-03
Pages: 4
Assignors
GHYSELEN, BRUNO
Executed: 2003-10-31
AULNETTE, CECILE
Executed: 2003-11-13
BATAILLOU, BENOIT
Executed: 2003-10-31
MAZURE, CARLOS
Executed: 2003-10-31
MORICEAU, HUBERT
Executed: 2003-12-18
Assignees
S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A.
PARC TECHNOLOGIQUE DES FONTAINES, CHEMIN DES FRANQUES, 38190 BERNIN, FRANCE
COMMISSARIAT A' L'ENERGIE ATOMIQUE (CEA)
ETABLISSEMENT PUBLIC DE CARACTERE SCIENTIFIQUE ET INDUSTRIEL, 31-33 RUE DE LA FEDERATION, 75752 PARIS, FRANCE
Covered Property
(1)
Method for Concurrently Producing at Least a Pair of Semiconductor Structures That Each Include at Least One Useful Layer on a Substrate