Patent Assignment
Reel/Frame 014490/0044
Assignment of Assignor's Interest
Recorded: 2004-04-05
Pages: 7
Assignors
BARROSO, LUIZ A.
Executed: 2001-06-11
GHARACHORLOO, KOUROSH
Executed: 2001-06-11
NOWATZYK, ANDREAS
Executed: 2004-03-18
RAVISHANKAR, MOSUR K.
Executed: 2001-06-11
STETS, ROBERT J., JR.
Executed: 2001-06-11
Assignee
HEWLETT-PACKARD DEVELOPMENT COMPANY, LP.
20555 SH 249, HOUSTON, TEXAS, 77070
Covered Property
(1)
Multiprocessor Cache Coherence System and Method in Which Processor Nodes and Input/Output Nodes Are Equal Participants
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
Assignment of Assignor's Interest
Jun 2, 2017
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
To: SK HYNIX INC.
Reel/Frame 042671/0448 →