Patent Assignment
Reel/Frame 042671/0448
Assignment of Assignor's Interest
Recorded: 2017-06-02
Pages: 5
Assignor
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Executed: 2017-05-19
Assignee
SK HYNIX INC.
2091, GYEONGCHUNG-DAERO, BUBAL-EUB, ICHEON-SI, GYEONGGI-DO, KOREA, REPUBLIC OF
Covered Properties
(8)
Method and System for Exclusive Two-Level Caching in a Chip-Multiprocessor
Scalable Architecture Based on Single-Chip Multiprocessing
System and Method for Limited Fanout Daisy Chaining of Cache Invalidation Requests in a Shared-Memory Multiprocessor System
System for Handling Coherence Protocol Races in a Scalable Shared Memory System Based on Chip Multiprocessing
System and Method for Limited Fanout Daisy Chaining of Cache Invalidation Requests in a Shared-Memory Multiprocessor System
Scalable Architecture Based on Single-Chip Multiprocessing
Multiprocessor Cache Coherence System and Method in Which Processor Nodes and Input/Output Nodes Are Equal Participants
Method and System for Exclusive Two-Level Caching in a Chip-Multiprocessor
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.