IP Library › Assignment 014557/0787
Patent Assignment
Reel/Frame 014557/0787

Assignment of Assignor's Interest

Recorded: 2004-04-23 Pages: 4
Assignors
BERNE, CECILE
Executed: 2004-01-19
GHYSELEN, BRUNO
Executed: 2004-01-20
LAGAHE, CHRYSTELLE
Executed: 2004-01-20
MAURICE, THIBAUT
Executed: 2004-01-19
Assignees
S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A.
PARC TECHNOLOGIQUE DES FONTAINES CHEMIN DES FRANQUES, 38190 BERNIN, FRANCE
COMMISSARIAT A L'ENERGIE ATOMIQUE (CEA)
ETABLISSEMENT PUBLIC DE CARACTERE SCIENTIFIQUE ET INDUSTRIEL, 31-33 RUE DE LA FEDERATION, 75752 PARIS, FRANCE
Covered Property (1)
Two-Stage Annealing Method for Manufacturing Semiconductor Substrates
Patent: 6,936,523 →
Application: 10/733,431 →
Publication: US 2004/0161904
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Mar 4, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027800/0911 →