Patent Assignment
Reel/Frame 027800/0911
Change of Name
Recorded: 2012-03-04
Pages: 10
Assignor
S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Executed: 2011-09-06
Assignee
SOITEC
PARC TECHNOLOGIQUE DES FONTAINES, CHEMIN DES FRANQUES, 38190 BERNIN, FRANCE
Covered Properties
(160)
Fabrication of Substrates with a Useful Layer of Monocrystalline Semiconductor Material
Fabrication of Substrates with a Useful Layer of Monocrystalline Semiconductor Material
Fabrication of Substrates with a Useful Layer of Monocrystalline Semiconductor Material
Method for Producing an Useful Layer on a Substrate by Sequentially Implanting Helium and Then Hydrogen Species into a Donor Substrate Followed by Thermal Treatment Process After Detaching the Useful Layer from Donor Substrate.
Application:
11/446,357 →
Publication:
US US20060223283A1
Substrate Cutting Device and Method
Method of Manufacturing a Material Compound Wafer
Application:
11/617,345 →
Publication:
US US20070105246A1
Hemt Piezoelectric Structures with Zero Alloy Disorder
Application:
11/684,925 →
Publication:
US US20070164299A1
Method of Fabricating an Epitaxially Grown Layer
Optoelectronic Substrate and Methods of Making Same
Optoelectronic Substrate and Methods of Making Same
Application:
12/424,868 →
Publication:
US US20090200569A1
Method of Fabricating a Release Substrate
Application:
13/151,358 →
Publication:
US US20110233733A1
Substrate with Determinate Thermal Expansion Coefficient
Application:
12/983,543 →
Publication:
US US20110094668A1
Method of Reducing Roughness of a Thick Insulating Layer
Method for Making a Composite Substrate and Composite Substrate According to the Method
Double Plasma Utbox
Application:
11/755,560 →
Publication:
US US20080145650A1
Patterned Thin Soi
Application:
13/078,403 →
Publication:
US US20110180912A1
Method of Bonding Two Substrates
Method for Manufacturing Compound Material Wafer and Corresponding Compound Material Wafer
Application:
11/850,170 →
Publication:
US US20080268621A1
Chemical-Mechanical Polishing Method and Apparatus
Application:
11/851,830 →
Publication:
US US20070298606A1
Method and Installation for Fracturing a Composite Substrate Along an Embrittlement Plane
Multiple Gate Field Effect Transistor Structure and Method for Fabricating Same
Application:
12/200,400 →
Publication:
US US20090121288A1
Relaxation of Strained Layers
Application:
13/056,572 →
Publication:
US US20110143522A1
Methods for Relaxation and Transfer of Strained Layers and Structures Fabricated Thereby
Method of Producing an Soi Structure with an Insulating Layer of Controlled Thickness
Controlled Temperature Implantation
Method for Polishing Heterostructures
Application:
12/524,246 →
Publication:
US US20110117740A1
Process for Fabricating a Substrate Comprising a Deposited Buried Oxide Layer
Doped Substrate to Be Heated
Method for Fabricating a Locally Passivated Germanium-on-Insulator Substrate
Method for Bonding Two Substrates
Application:
12/556,381 →
Publication:
US US20100155882A1
Method of Fabricating a Composite Structure with a Stable Bonding Layer of Oxide
Application:
12/663,693 →
Publication:
US US20100190000A1
Charge Reservoir Structure
Methods of Manufacturing Semiconductor Structures and Semiconductor Structures Obtained by Such Methods
Application:
12/989,532 →
Publication:
US US20110042780A1
Substrate Comprising Different Types of Surfaces and Method for Obtaining Such Substrates
Application:
12/989,474 →
Publication:
US US20110037150A1
Method of Manufacturing a Structure Comprising a Substrate and a Layer Deposited on One of Its Faces
Application:
12/672,797 →
Publication:
US US20110192343A1
Method of Producing a Structure by Layer Transfer
Method for Making a Substrate of the Semiconductor on Insulator Type with an Integrated Ground Plane
Precise Oxide Dissolution
Application:
12/677,083 →
Publication:
US US20100193899A1
Method for Heating a Wafer by Means of a Light Flux
Device Comprising a Field-Effect Transistor in a Silicon-On-Insulator
PSEUDO-INVERTER CIRCUIT ON SeOI
Method for Manufacturing a Semiconductor Substrate
Method for Manufacturing Heterostructures
Method for Fabricating a Semiconductor Substrate
Nano-Sense Amplifier
Positioning of Semiconductor Substrates in a Furnace
Application:
12/830,988 →
Publication:
US US20110020957A1
Substrates for Monolithic Optical Circuits and Electronic Circuits
Processing for Bonding Two Substrates
Application:
12/811,209 →
Publication:
US US20110000612A1
Sram-Type Memory Cell
Heterostructure for Electronic Power Components, Optoelectronic or Photovoltaic Components
Application:
12/956,675 →
Publication:
US US20110127581A1
Method for Fabricating a Semiconductor on Insulator Type Substrate
Method for Manufacturing a Layer of Gallium Nitride or Gallium and Aluminum Nitride
Etching Composition, in Particular for Strained or Stressed Silicon Materials, Method for Characterizing Defects on Surfaces of Such Materials and Process of Treating Such Surfaces with the Etching Composition
Germanium Layer Polishing
Apparatus for Manufacturing Semiconductor Devices
Application:
12/888,251 →
Publication:
US US20110308721A1
Apparatus for Manufacturing Semiconductor Devices
Application:
13/306,719 →
Publication:
US US20120067524A1
Mixed Trimming Method
Application:
12/933,966 →
Publication:
US US20110117691A1
Progressive Trimming Method
Semiconductor Device Having an Ingan Layer
METHOD OF CONTROLLING A DRAM MEMORY CELL ON THE SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER
Application:
12/898,230 →
Publication:
US US20110134690A1
Temporary Substrate, Transfer Method and Production Method
Method for Molecular Adhesion Bonding with Compensation for Radial Misalignment
Low-Temperature Bonding Process
Process for Measuring an Adhesion Energy, and Associated Substrates
Method for Molecular Adhesion Bonding at Low Pressure
Dram Memory Cell Having a Vertical Bipolar Injector
Manufacture of Thin Silicon-on-Insulator (Soi) Structures
Method for Routing a Chamfered Substrate
Process for Fabricating a Heterostructure with Minimized Stress
Flash Memory Cell on Seoi Having a Second Control Gate Buried Under the Insulating Layer
Arrays of Transistors with Back Control Gates Buried Beneath the Insulating Film of a Semiconductor-on-Insulator Substrate
Memory Cell with a Channel Buried Beneath a Dielectric Layer
Devices and Methods for Comparing Data in a Content-Addressable Memory
Method for Making a Structure Comprising a Step for Implanting Ions in Order to Stabilize the Adhesive Bonding Interface
Application:
12/997,835 →
Publication:
US US20110165758A1
Stiffening Layers for the Relaxation of Strained Layers
DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER
Process for Fabricating a Multilayer Structure with Trimming Using Thermo-Mechanical Effects
Uv Absorption Based Monitor and Control of Chloride Gas Stream
Device Having a Contact Between Semiconductor Regions Through a Buried Insulating Layer, and Process for Fabricating Said Device
DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER
Process for Locally Dissolving the Oxide Layer in a Semiconductor-on-Insulator Type Structure
Method for Forming a Ge on Iii/V-on-Insulator Structure
Method of Detaching Semi-Conductor Layers at Low Temperature
Method for Producing a Stack of Semi-Conductor Thin Films
Surface Treatment for Molecular Bonding
Method of Fabricating a Back-Illuminated Image Sensor
Methods for Manufacturing Multilayer Wafers with Trench Structures
Ingot Formed from Basic Ingots, Wafer Made from Said Ingot and Associated Method
Application:
13/128,609 →
Publication:
US US20110214806A1
Method of Thinning a Structure
Method for Treating a Part Made from a Decomposable Semiconductor Material
Methods of Making Substrate Structures Having a Weakened Intermediate Layer
Process to Dissolve the Oxide Layer in the Peripheral Ring of a Structure of Semiconductor-on-Insulator Type
Application:
13/145,313 →
Publication:
US US20110275226A1
Finishing Method for Manufacturing Substrates in the Field of Electronics
Application:
13/141,033 →
Publication:
US US20110256730A1
Finishing Method for a Silicon on Insulator Substrate
Direct Bonding Method with Reduction in Overlay Misalignment
Method for Manufacturing a Heterostructure Aiming at Reducing the Tensile Stress Condition of a Donor Substrate
Method of Producing a Heterostructure with Local Adaptation of the Thermal Expansion Coefficient
Detachable Substrate and Processes for Fabricating and Detaching Such a Substrate
Method for Molecular Bonding of Silicon and Glass Substrates
Process for Realizing a Connecting Structure
Method to Thin a Silicon-on-Insulator Substrate
Process for Cleaving a Substrate
Fully Depleted Soi Device with Buried Doped Layer
Semiconductor Structure with Smoothed Surface and Process for Obtaining Such a Structure
Method for Recycling a Source Substrate
Application:
13/368,028 →
Publication:
US US20120199956A1
Process for Treating a Semiconductor-on-Insulator Structure
Methods for High Volume Manufacture of Group Iii-V Semiconductor Materials
High Volume Delivery System for Gallium Trichloride
Application:
12/305,434 →
Publication:
US US20090223441A1
Methods for in-Situ Chamber Cleaning Process for High Volume Manufacture of Semiconductor Materials
Application:
12/602,740 →
Publication:
US US20100180913A1
Abatement of Reaction Gases from Gallium Nitride Deposition
Gallium Trichloride Injection Scheme
Epitaxial Methods and Templates Grown by the Methods
Methods for Improving the Quality of Epitaxially-Grown Semiconductor Materials
Methods for Improving the Quality of Group Iii-Nitride Materials and Structures Produced by the Methods
Temperature-Controlled Purge Gate Valve for Chemical Vapor Deposition Chamber
Equipment for High Volume Manufacture of Group Iii-V Semiconductor Materials
Apparatus for Delivering Precursor Gases to an Epitaxial Growth Substrate
Thermalization of Gaseous Precursors in Cvd Reactors
Modular and Readily Configurable Reactor Enclosures and Associated Function Modules
Application:
12/937,153 →
Publication:
US US20110033610A1
Methods for Improving the Quality of Structures Comprising Semiconductor Materials
Methods for Improving the Quality of Structures Comprising Semiconductor Materials
External Gas Injectors for Cvd Systems Including Active and Passive Heating Elements
Application:
13/145,290 →
Publication:
US US20110277681A1
High Volume Delivery System for Gallium Trichloride
Application:
12/303,950 →
Publication:
US US20100242835A1
Fabrication of Substrates with a Useful Layer of Monocrystalline Semiconductor Material
Fabrication of Substrates with a Useful Layer of Monocrystalline Semiconductor Material
Fabrication of substrates with a useful layer of monocrystalline semiconductor material
Application:
10/458,471 →
Publication:
US US20030232487A1
Method for Producing a High Quality Useful Layer on a Substrate
Substrate Cutting Device and Method
Substrate Cutting Device and Method
Method of Manufacturing a Material Compound Wafer
High electron mobility transistor piezoelectric structures
Application:
11/004,411 →
Publication:
US US20060054926A1
Method of Fabricating an Epitaxially Grown Layer
Optoelectronic Substrate and Methods of Making Same
Method of Fabricating a Release Substrate
Method of Fabricating a Release Substrate
Substrate with Determinate Thermal Expansion Coefficient
Method of Reducing Roughness of a Thick Insulating Layer
Patterned Thin Soi
Bonding Interface Quality by Cold Cleaning and Hot Bonding
Methods and Structures for Relaxation of Strained Layers
Methods for Relaxation and Transfer of Strained Layers and Structures Fabricated Thereby
Method for Manufacturing a Layer of Gallium Nitride or Gallium and Aluminum Nitride
Temporary Substrate, Transfer Method and Production Method
Application:
12/897,409 →
Publication:
US US20120012244A1
Method for Molecular Adhesion Bonding at Low Pressure
Application:
12/910,081 →
Method of Producing a Plate-Shaped Structure, in Particular, from Silicon, Use of Said Method and Plate-Shaped Structure Thus Produced, in Particular from Silicon
Method for Making a Plate-Like Detachable Structure, in Particular Made of Silicon, and Use of Said Method
Application:
12/087,093 →
Publication:
US US20090301995A1
Method for Treating Substrates for Microelectronics and Substrates Obtained by Said Method
Method for Treating Substrates for Microelectronics and Substrates Obtained by Said Method
Two-Stage Annealing Method for Manufacturing Semiconductor Substrates
Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
Application:
10/784,017 →
Publication:
US US20040192067A1
Methods for preparing a bonding surface of a semiconductor wafer
Application:
10/875,233 →
Publication:
US US20050218111A1
Methods for Preparing a Bonding Surface of a Semiconductor Wafer
Methods for minimizing defects when transferring a semiconductor useful layer
Application:
11/020,057 →
Publication:
US US20060040470A1
Methods for Minimizing Defects When Transferring a Semiconductor Useful Layer
Thermal treatment of a semiconductor layer
Application:
11/233,318 →
Publication:
US US20060014363A1
Methods for making substrates and substrates formed therefrom
Application:
11/505,668 →
Publication:
US US20070141803A1
Precise Oxide Dissolution
Application:
13/409,888 →
Publication:
US US20120190170A1
Method for treating substrates for microelectronics and substrates obtaining by said method
Application:
10/069,163 →
Substrate Holder and Clipping Device
Application:
12/880,806 →
Publication:
US US20110101249A1
Gallium Trichloride Injection Scheme
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 12, 2010
From: KERDILES, SEBASTIEN; MICHEL, WILLY; SCHWARZCNHACH, WALTER; DELPRAT, DANIEL
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 023764/0592 →
Assignment of Assignor's Interest
Mar 28, 2011
From: LETERTRE, FABRICE; GHYSELEN, BRUNO; RAYSSAC (BY PIERRE RAYSSAC, PARENT AND LEGAL REPRESENTATIVE OF OLIVIER RAYSSAC, DECEASED), OLIVIER; RAYSSAC (BY GISELE RAYSSAC, PARENT AND LEGAL REPRESENTATIVE OF OLIVIER RAYSSAC, DECEASED), OLIVIER
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 026034/0776 →
Assignment of Assignor's Interest
Oct 14, 2011
From: LETERTRE, FABRICE; GHYSELEN, BRUNO; RAYSSAC (DECEASED), BY PIERRE RAYSSAC AND GISELE RAYSSAC, PARENTS AND LEGAL REPRESENTATIVES, OLIVIER
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 027064/0385 →
Assignment of Assignor's Interest
Nov 30, 2011
From: LETERTRE, FABRICE; GHYSELEN, BRUNO; RAYSSAC (DECEASED), BY PIERRE RAYSSAC AND GISELE RAYSSAC, PARENTS AND LEGAL REPRESENTATIVES, OLIVIER
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 027298/0848 →
Patent Security Agreement
Oct 5, 2017
From: XPEDITION ARCHERY, LLC; GENERAL ECOLOGY, INC.
To: NEWSTAR FINANCIAL, INC.
Reel/Frame 044129/0485 →