Method for forming a Ge on III/V-on-insulator structure
View Patent ↗The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
1. A semiconductor structure including an N Field-Effect Transistor (NFET) formed in a germanium on III/V-On-Insulator (Ge-III/V-OI) structure comprising a support substrate, an insulating layer on the support substrate, at least one layer of III/V material on the insulating layer, and a germanium layer on the at least one layer of III/V material, wherein the NFET comprises:
a gate in a cavity in the germanium layer extending to the at least one layer of III/V material, the gate being insulated from the germanium layer and the III/V layer(s) by a high-K dielectric material;
a source region in the germanium layer on a first side portion of the cavity; and
a drain region in the germanium layer on an opposite side portion of the cavity.
2. The semiconductor structure of claim 1 , further comprising a P Field Effect Transistor (PFET) formed in the Ge-III/V-OI structure, wherein the PFET transistor comprises:
an island on the germanium layer, the island comprising a gate insulated from the germanium layer by a high-K dielectric material;
a source region in the germanium layer on a first side of the island; and
a drain region in the germanium layer on another other side of the island.
3. The semiconductor structure according to claim 1 , wherein the germanium layer is relaxed.
4. The semiconductor structure according to claim 1 , wherein the III/V material is InP, AsGa, InAs or InGaAs.
5. The semiconductor structure according to claim 1 , wherein the III/V material is InGaAs.
6. The semiconductor structure according to claim 1 , wherein the support substrate is made of silicon and the insulating layer is an oxide.
7. The semiconductor structure according to claim 1 , further comprising a cavity in the germanium layer extending to the at least one layer of III/V material.
8. The semiconductor structure according to claim 7 , further comprising a high-K dielectric material in the cavity.
9. The semiconductor structure according to claim 8 , further comprising a metal layer on the high-K dielectric material.
10. A method for manufacturing an N Field-Effect Transistor (NFET) in a germanium on III/V-On-Insulator (Ge-III/V-OI) structure comprising a support substrate, an insulating layer on the support substrate, at least one layer of III/V material on the insulating layer, and a germanium layer on the at least one layer of III/V material the NFET comprising a gate in a cavity in the germanium layer extending to the at least one layer of III/V material, the gate being insulated from the germanium layer and the III/V layer(s) by a high-K dielectric material, a source region in the germanium layer on a first side portion of the cavity, and a drain region in the germanium layer on an opposite side portion of the cavity, wherein the method comprises:
providing a cavity in the germanium layer of the Ge-III/V-OI structure extending to the layer of III/V material;
depositing in the cavity a high-K dielectric material and a gate, with the gate being insulated from the germanium layer and the layer of III/V material by the high-K dielectric material; and
implanting a source region and a drain region in the germanium layer on each side of the cavity.
11. A method for manufacturing a P Field-Effect Transistor (PFET) formed in a Ge-III/V-OI structure comprising a support substrate, an insulating layer on the support substrate, at least one layer of III/V material on the insulating layer, and a germanium layer on the at least one layer of III/V material, the PFET transistor comprising an island on the germanium layer, the island comprising a gate insulated from the germanium layer by a high-K dielectric material, a source region in the germanium layer on a first side of the island, and a drain region in the germanium layer on another other side of the island, wherein the method comprises:
forming an island on the germanium layer of the Ge-III/V-OI structure by depositing a high-K dielectric material and a gate, with the gate being insulated from the germanium layer by the high-K dielectric material; and
implanting a source region and a drain region in the germanium layer on a side of the island.
12. The method according to claim 11 , wherein the Ge-III/V-OI structure is formed by growing a silicon germanide buffer layer of lattice adaptation on the donor substrate, with the relaxed germanium layer being grown on the silicon germanide buffer layer, thereafter forming a cavity in the buffer layer that extends to the germanium layer before forming the island, with the gate being insulated from the buffer layer by the high-K dielectric material.
13. The method according claim 11 , which further comprises partially recessing the germanium layer before forming the island.