Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device

1. A process for fabricating a semiconductor device on a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, and the semiconductor device comprises a first conducting region of a memory cell in the thin layer and a second conducting region in the base substrate,

wherein the process comprises:

providing an access line in the base substrate beneath the buried insulating layer for forming the second conducting region, wherein the access line comprises a buried bit line or a buried source line, and wherein the access line is isolated by a lateral and underlining isolation well of opposite conductivity of the access line; and

providing a contact immediately below the first conducting region for connecting the first conducting region to the access line.

2. The process according to claim 1 , wherein the contact is formed by:

etching the semiconductor-on-insulator substrate in order to form therein a trench extending through the first conducting region and extending beyond the buried insulating layer to the second conducting region; and

filling the trench with an interconnect material.

3. The process according to claim 2 , wherein the interconnect material is a predoped semiconductor material.

4. The process according to claim 2 , wherein the interconnect material is a semiconductor material and which further includes a step of doping the semiconductor material in the trench.

5. The process according to claim 4 , wherein the doping of the semiconductor material in the trench is performed by an annealing operation that diffuses dopants in the trench.

6. The process according to claim 1 , wherein the first conducting region is a drain region or a source region of a transistor.

7. The process according to claim 1 , wherein the second conducting region is a back control gate region of a transistor and the first conducting region belongs to a back control gate drive line.

8. A process for fabricating a semiconductor device, the process comprising:

forming a base substrate;

forming an access line;

forming a buried insulator layer over the base substrate and the access line;

forming a thin layer of semiconductor material on the buried insulator layer, wherein the thin layer of semiconductor material is separated from the base substrate by the buried insulator layer;

forming first conducting regions of a plurality of cells within the thin layer of semiconductor material, wherein the access line extends beneath the plurality of cells to provide shared addressing of the plurality of cells, and wherein the access line is isolated by a lateral and underlining isolation well of opposite conductivity of the access line;

forming interconnects through the buried insulator layer to connect corresponding first conducting regions within the thin layer of semiconductor material to the access line.

9. The process of claim 8 , wherein forming the access line further comprises forming the access line of a conducting material.

10. The process of claim 9 , wherein forming the access line of the conducting material further comprises forming the access line of a doped semiconductor material.

11. The process of claim 8 , wherein forming the interconnects further comprises forming trenches extending from the first conducting regions through the buried insulator layer to the access line.

12. The process of claim 11 , wherein forming the interconnects further comprises filling the trenches with an interconnect material.

13. The process of claim 12 , wherein filling the trenches with the interconnect material further comprises filling the trenches with a metallic interconnect material.

14. The process of claim 12 , wherein filling the trenches with the interconnect material further comprises filling the trenches with a semiconductor material.