IP Library Granted Patent US 8,236,593
Granted Patent B2
US 8,236,593 · App. 12/600,120 · Granted Aug 7, 2012

Methods for improving the quality of epitaxially-grown semiconductor materials

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Quick Facts
Patent No.
US 8,236,593
App. No.
12/600,120
Granted
Aug 7, 2012
Kind
B2
Abstract

The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.

Claims (31)

1. A method for reducing defects and dislocations during fabrication of a semiconductor structure comprising:

fabricating the semiconductor structure with a semiconductor layer having an exposed surface and comprising a semiconductor material, the exposed surface of the semiconductor material having a plurality of defects and dislocations;

capping a plurality of the exposed defects and dislocations by depositing a masking material so as to form caps comprising the masking material, the masking material of the caps replacing a portion of the semiconductor layer at the locations of the capped surface defects and dislocations;

removing the deposited masking material from the exposed surface of the semiconductor material by chemical mechanical polishing;

smoothing roughness of the exposed surface of the semiconductor material subsequent to the removing of the deposited masking material; and

epitaxially growing a following semiconductor layer on the smoothed exposed surface.

2. The method of claim 1 wherein the caps are sized and arranged to facilitate epitaxial lateral overgrowth of the following layer over the caps.

3. The method of claim 1 wherein capping the defects and dislocations further comprises:

forming pits at some or all of the surface defects and dislocations, the pits extending into the semiconductor layer; and

occluding the surface openings of the pits by substantially completely filling the pits with the masking material.

4. The method of claim 3 wherein forming pits further comprises etching the exposed surface preferentially at the defects or dislocations.

5. The method of claim 3 wherein occluding the surface openings further comprises:

depositing the masking material on the etched exposed surface;

removing those portions of the masking material that are deposited on the etched exposed surface but are not occluding surface openings of the pits.

6. The method of claim 1 wherein the following semiconductor layer comprises a III-V material on the exposed surface under conditions favoring epitaxial lateral overgrowth (ELO) over the caps.

7. The method of claim 6 wherein the steps of capping and growing are repeated one or more times.

8. The method of claim 6 wherein the masking material is selected to promote ELO of the following layer.

9. The method of claim 6 wherein the caps are sized and arranged to promote ELO of the following layer.

10. The method of claim 6 wherein the following layer comprises a III nitride material.

11. The method of claim 1 wherein the semiconductor material comprises Group III nitrides, and wherein the smoothing comprises a mass transport regrowth process.

12. The method of claim 11 wherein the mass transport regrowth process comprises heating in an atmosphere comprising NH 3 and H 2 .

13. The method of claim 1 wherein the steps of capping and growing are repeated one or more times.

14. The method of claim 1 wherein the steps of capping, polishing, smoothing, and growing are repeated one or more times.

15. A method for reducing defects and dislocations during fabrication of a semiconductor structure comprising:

fabricating the semiconductor structure with a semiconductor layer comprising a semiconductor material having an exposed surface, the exposed surface of the semiconductor material having a plurality of defects and dislocations;

forming pits at some or all of the surface defects and dislocations by etching, with the pits extending into the semiconductor layer which is removed by the etching;

substantially completely filling the pits by depositing a masking material to replace the semiconductor material that was etched away;

removing the deposited masking material from the exposed surface of the semiconductor material by chemical mechanical polishing;

smoothing roughness of the exposed surface of the semiconductor material subsequent to the removing of the deposited masking material; and

epitaxially growing a following semiconductor layer on the smoothed exposed surface.

16. The method of claim 15 wherein the smoothing comprises heating in an atmosphere comprising NH 3 and H 2 .

Assignments (3)
CHANGE OF NAME Recorded Mar 4, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027800/0911 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2009
From: ARENA, CHANTAL
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 023662/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2009
From: MAHAJAN, SUBHASH; HAN, ILSU
To: ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY
Reel/Frame 023663/0050 →