MULTIPLE GATE FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING SAME
The present invention relates to a Multiple Gate Field Effect Transistor structure and a method for fabricating same. The Multiple Gate Field Effect Transistor structure includes a fin structure made from at least one active semiconductor layer of a silicon on insulator (SOI) structure on a buried insulator of the structure. The Multiple Gate Field Effect Transistor structure also includes an insulator of at least one high-k layer of a material having a dielectric constant that is higher than silicon oxide. This has the advantage that the high-k layer acts as a better etch stop than silicon oxide during formation and cleaning of the fin resulting in a lower recess and undercut effect on the socket of the fin. This leads to a higher stability of the formed fin and enables a smooth finishing of the fin by etching and cleaning steps.
1 . A method for fabricating a Multiple Gate Field Effect Transistor structure, which comprises:
providing a silicon on insulator (SOI) substrate comprising at least one active semiconductor layer, a buried insulator and a carrier substrate, and
forming from the semiconductor layer a fin structure on the insulator, with the fin structure forming a region for a transistor channel of the multiple gate field effect transistor structure,
wherein the insulator comprises at least one high-k layer of a material having a dielectric constant that is higher than silicon oxide.
2 . The method of claim 1 , wherein the semiconductor layer from which the fin structure is formed includes at least one layer of silicon, strained silicon, SiGe, SiC, Ge or a Group III-V compound.
3 . The method of claim 1 , wherein the insulator comprises at least one silicon nitride layer.
4 . The method of claim 1 , wherein the insulator comprises a silicon oxide layer that is positioned between the high-k layer and the semiconductor layer of the SOI substrate.
5 . The method of claim 1 , wherein the insulator comprises a silicon oxide layer positioned between the high-k layer and the carrier substrate of the SOI substrate.
6 . The method of claim 1 , wherein the insulator comprises a layer stack that includes a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer.
7 . The method of claim 6 , wherein the silicon nitride layer is formed with a thickness of 10 to 200 nm.
8 . The method of claim 6 , wherein the upper silicon oxide layer is formed with a thickness of 2 to 20 nm.
9 . The method of claim 6 , wherein the lower silicon oxide layer is formed with a thickness of about 10 to 100 nm.
10 . The method of claim 1 , wherein the forming of the fin structure comprises an over-etch of the insulator.
11 . A Multiple Gate Field Effect Transistor (MuGFET) structure having a fin structure for forming therein a transistor channel, the fin structure comprised of at least one active semiconductor layer of a silicon on insulator (SOI) structure on a buried insulator of the structure, wherein the insulator comprises at least one high-k layer of a material having a dielectric constant that is higher than silicon oxide.
12 . The MuGFET structure of claim 11 , wherein the insulator comprises at least one silicon nitride layer.
13 . The MuGFET structure of claim 11 , wherein the insulator comprises silicon oxide and is positioned between the high-k layer and the part of the fin structure formed from the semiconductor layer of the SOI substrate.
14 . The MuGFET structure of claim 11 , wherein and the insulator comprises a silicon oxide layer that is positioned between the high-k layer and a carrier substrate of the SOI substrate.
15 . The MuGFET structure of claim 11 , wherein the insulator comprises a stack that includes a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer.
16 . The MuGFET structure of claim 15 , wherein the silicon nitride layer has a thickness of 10 to 200 nm.
17 . The MuGFET structure of claim 15 , wherein the upper silicon oxide layer has a thickness of 3 to 20 nm.
18 . The MuGFET structure of claim 15 , wherein the lower silicon oxide layer has a thickness of about 10 to 100 nm.