IP Library Patent Application 11446357
Patent Application
App. No. 11/446,357

Method for producing a high quality useful layer on a substrate

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Quick Facts
Patent No.
US None
App. No.
11/446,357
Abstract

A method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer. The implanting step is conducted to minimize low-frequency roughness at the weakened zone. Next, the method includes bonding a support substrate to the face of the donor substrate, and detaching the useful layer from the donor substrate along the weakened zone. A structure is thus formed that includes the useful layer on the support substrate with the useful layer presenting a surface for further processing. The technique also includes thermally treating the structure to minimize high-frequency roughness of the surface of the useful layer. The result is a surface having sufficient smoothness so that chemical mechanical polishing (CMP) is not needed.

Claims (27)

1 . A method for producing a high quality useful layer of semiconductor material on a substrate, which comprises:

implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer;

bonding a support substrate to the face of the donor substrate;

detaching the useful layer from the donor substrate along the weakened zone to form a structure that includes the useful layer on the support substrate with the useful layer presenting a useful layer surface for further processing, wherein the different atomic species are implanted to minimize low-frequency roughness of the useful layer surface; and

thermally treating the structure to minimize high-frequency roughness of the useful layer surface to thus provide the surface having sufficient smoothness to be suitable for use in microelectronic or optoelectronic applications without conducting a chemical mechanical polishing of the useful layer surface.

2 . The method of claim 1 , wherein the different atomic species are implanted so that the detachment of the useful layer at the weakened zone provides the useful layer surface with a low-frequency roughness of less than about 5 Å.

3 . The method of claim 2 , wherein the low-frequency roughness if measured over spatial periods of substantially between 3 and 15 μm.

4 . The method of claim 1 , further comprising conducting at least one of a simple or stabilized oxidation process on the useful layer surface after the thermal treatment, wherein a chemical mechanical polishing step is not conducted prior to the thermal treatment and the oxidation process.

5 . The method of claims 1 , wherein the at least two different atomic species comprises helium species and hydrogen species, and implanting comprises sequentially implanting the helium species and then the hydrogen species.

6 . The method of claim 1 , wherein the thermal treatment is a rapid thermal annealing process carried out at a temperature of between about 800° C. and 1400° C.

7 . The method of claim 6 , wherein the rapid thermal annealing process is conducted in an atmosphere comprising pure argon or hydrogen or a mixture thereof.

8 . The method of claim 1 , which further comprises conducting at least one stabilized oxidation process on the structure.

9 . The method of claim 8 , wherein the stabilized oxidation process comprises successive implementations of an oxidation operation, an annealing operation, and a deoxidation operation.

10 . The method of claim 9 , wherein the annealing operation comprises conducting the annealing operation for about two hours at a temperature of about 1100° C.

11 . The method of claim 8 , which further comprises conducting a rapid thermal annealing process on the structure prior to or after the stabilized oxidation process.

12 . The method of claim 8 , which further comprises conducting a plurality of both rapid thermal annealing and stabilized oxidation processes on the structure.

13 . The method of claim 1 , which further comprises at least one simple oxidation operation including an oxidation operation followed by a deoxidation operation of the structure.

14 . The method of claim 13 , which further comprises conducting a rapid thermal annealing process on the useful layer surface.

15 . A method for producing a high quality useful layer of semiconductor material on a substrate, which comprises:

sequentially implanting at least helium species and then hydrogen species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer;

bonding a support substrate to the face of the donor substrate;

detaching the useful layer from the donor substrate along the weakened zone to form a structure that includes the useful layer on the support substrate with the useful layer presenting a useful layer surface for further processing, wherein the different atomic species are implanted to minimize low-frequency roughness of the useful layer surface; and

thermally treating the structure to minimize high-frequency roughness of the useful layer surface to thus provide sufficient smoothness so that chemical mechanical polishing of the useful layer surface is not required.

16 . The method of claim 15 , wherein the helium species is implanted at a dose of between about 0.5×10 16 cm −2 and about 1.5×10 16 cm −2 .

17 . The method of claim 16 , wherein the helium species is implanted at a dose of about 0.9×10 16 cm −2 or less.

18 . The method of claim 17 , wherein the hydrogen species is implanted at a dose of between about 0.5×10 16 cm −2 and about 0.9×10 16 cm −2 .

19 . The method of claim 15 , wherein the hydrogen species is implanted at a dose of between about 0.5×10 16 cm −2 and about 2.5×10 16 cm −2 .

Assignments (2)
CHANGE OF NAME Recorded Mar 4, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027800/0911 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 29, 2012
From: MALEVILLE, CHRISTOPHE; NEYRET, ERIC; BEN MOHAMED, NADIA
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A.
Reel/Frame 027786/0042 →