IP Library Patent Application 13141033
Patent Application
App. No. 13/141,033

FINISHING METHOD FOR MANUFACTURING SUBSTRATES IN THE FIELD OF ELECTRONICS

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Quick Facts
Patent No.
US None
App. No.
13/141,033
Abstract

The invention relates to a method for finishing the surface of semiconducting substrate that has a set of layers and a useful semiconducting layer on at least one of the faces of the substrate, wherein the useful layer has a rough free surface. The method smoothes out the rough free surface of the useful layer by creating a protective layer covering the surface of the useful layer with a thickness 1 to 3 times larger than the peak-to-valley distance of the surface of the useful layer, at least one polishing-oxidation sequence that includes the successive steps of polishing the surface of the protective layer, with the polishing being adjusted so as not to attack the useful layer, and performing a thermal oxidation with supply of oxygen gas of the substrate in order to transform a portion of the useful layer into an oxide layer and reduce the roughness of the surface of the useful layer.

Claims (19)

1 .- 12 . (canceled)

13 . A method for finishing the surface of a semiconductor substrate having top and bottom faces and comprising a set of layers with a useful semiconductor layer on at least one of the faces, wherein the useful layer has a rough surface, which method comprises smoothing out the rough surface of the useful layer by:

creating a protective layer covering the rough surface of the useful layer with the protective layer having a thickness that is 1 to 3 times larger than the peak-to-valley distance profile of the rough surface of the useful layer; and

conducting at least one polishing-oxidation sequence which comprises:

polishing the protective layer without attacking the useful layer, and

performing a thermal oxidation with oxygen in order to transform a portion of the useful layer into an oxide layer to thus reduce the roughness of the surface of the useful layer.

14 . The method according to claim 13 , wherein the protective layer comprises an oxide.

15 . The method according to claim 14 , wherein the oxide is deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition).

16 . The method according to claim 14 , wherein the oxide is provided by thermal oxidation with oxygen.

17 . The method according to claim 13 , wherein the protective layer comprises a nitride.

18 . The method according to claim 17 , wherein the nitride is deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition).

19 . The method according to claim 17 , wherein the nitride is provided by thermal nitridation with nitrogen.

20 . The method according to claim 13 , wherein the polishing is a selective polishing of only the protective layer such that the peaks of the useful layer can be exposed.

21 . The method according to claim 13 , wherein the polishing is a non-selective polishing conducted in a manner so as to only remove part of the protective layer without exposing the useful layer.

22 . The method according to claim 13 , wherein the protective layer is formed at a thickness that is about 1.8 times larger than the peak-to-valley distance of the rough surface of the useful layer.

23 . The method according to claim 13 , wherein the useful layer comprises silicon or germanium.

24 . The method according to claim 13 , wherein the useful layer comprises germanium, and oxide layer is a germanium oxide layer formed by thermal oxidation of the useful layer at a temperature between 450 and 5 50 ° C.

25 . The method according to claim 24 , wherein the polishing is non-aqueous polishing or dry polishing.

26 . The method according to claim 13 , wherein the useful layer comprises silicon, and the oxide layer is a silicon oxide layer formed by wet thermal oxidation at a temperature of less than 600° C.

Assignments (2)
CHANGE OF NAME Recorded Mar 4, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027800/0911 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2011
From: RIOU, GREGORY
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 026612/0089 →