SRAM-type memory cell

1. A SRAM-type memory cell comprising:

a semiconductor on insulator substrate comprising a thin film of semiconductor material separated from a base substrate by an insulating layer; six transistors comprising two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters, with each of the transistors comprising a drain region and a source region arranged in the thin film, a channel extending between the source region and the drain region and a front gate situated above the channel,

wherein each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential, and wherein the first and second potentials are modulated according to the type of cell control operation.

2. The memory cell according to claim 1 , wherein the access transistors and conduction transistors are NFET transistors, the charge transistors are PFET transistors, and the back control gates of the access transistors are of N+ conductivity and the back control gates of the conduction transistors and charge transistors are of N+ conductivity.

3. The memory cell according to claim 1 , wherein the back control gates of the conduction transistors and charge transistors are arranged in the base substrate below the channel in a well of conductivity that is opposite to that of the back control gates.

4. The memory cell according to claim 1 , which is fully depleted.

5. The memory cell according to claim 1 , wherein the semiconductor on insulator substrate comprises a silicon on insulator substrate and the insulating layer is a buried oxide layer.

6. A memory array comprising a plurality of SRAM cells according to claim 1 , wherein the channel of each transistor has a minimal physical width but has an apparent width that can be modulated by the application of a potential to the back control gates of the transistors.

7. A method of fabricating an SRAM-type memory cell according to claim 1 , which comprises:

providing a semiconductor on insulator substrate comprising a thin film of semiconductor material separated from a base substrate by an insulating layer, and

forming back control gates in the base substrate by implantation of atomic species.

8. The method according to claim 1 , wherein a so-called “high” positive voltage and a so-called “low” positive or zero voltage less than the high voltage is defined to bias the back control gates of the transistors, and wherein, according to the type of cell control operation, a high voltage or a low voltage is dynamically applied to the back control gates of the transistors.

9. The method according to claim 8 , which further comprises, for a standby operation, applying a low voltage to the back control gates of the access transistors and to the back control gates of the conduction transistors and charge transistors.

10. The method according to claim 8 , which further comprises, for a read operation, applying a low voltage to the back control gates of the access transistors and a high voltage to the back control gates of the conduction transistors and charge transistors.

11. The method according to claim 8 , which further comprises, for a write operation, applying a high voltage to the back control gates of the access transistors and a low voltage to the back control gates of the conduction transistors and charge transistors.

12. The method of claim 8 , wherein the semiconductor on insulator substrate comprises a silicon on insulator substrate and the insulating layer is a buried oxide layer.