IP Library Granted Patent US 8,314,007
Granted Patent B2
US 8,314,007 · App. 12/943,693 · Granted Nov 20, 2012

Process for fabricating a heterostructure with minimized stress

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Quick Facts
Patent No.
US 8,314,007
App. No.
12/943,693
Granted
Nov 20, 2012
Kind
B2
Abstract

A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed.

Claims (35)

1. A process for fabricating a heterostructure comprising:

bonding a first wafer to a second wafer, wherein the first wafer has a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and the first wafer has an edge;

conducting a first trimming step in which an annular portion at the edge of the first wafer is at least partially reduced in thickness; and

conducting at least one bond-strengthening annealing step after the first trimming step;

wherein the first trimming step is conducted after the bonding step and before thinning of the first wafer and remaining annular portion.

2. The process according to claim 1 , wherein after the first trimming step, the first wafer has an annular edge portion with a thickness less than or equal to 55 μm.

3. A process for fabricating a heterostructure which comprises:

bonding a first wafer to a second wafer, wherein the first wafer has a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and the first wafer has an edge;

conducting a first trimming step in which an annular portion at the edge of the first wafer is at least partially reduced in thickness;

conducting at least one bond-strengthening annealing step;

conducting a second trimming step;

wherein the first trimming step is carried out after the bonding and before a first bond-strengthening annealing step, and the second trimming step is conducted after the first bond-strengthening annealing step but before a second bond-strengthening annealing step.

4. The process according to claim 3 , wherein the second bond-strengthening annealing step is carried out at a higher temperature than the first bond-strengthening annealing step.

5. The process according to claim 1 , wherein the first wafer is a silicon or SOI substrate.

6. The process according to claim 1 , wherein the at least one bond-strengthening anneal has a boat-in temperature of the heterostructure lower than 80° C.

7. The process according to claim 1 , wherein the at least one bond-strengthening anneal or anneals has a temperature ramp-up of about 1° C./min.

8. The process according to claim 1 , which further comprises forming an oxide layer on the bonding surface of the first wafer before the bonding of the two wafers.

9. The process according to claim 1 , which further comprises activating the bonding surface of at least one of the two wafers before bonding.

10. The process according to claim 1 , which further comprises conducting a thinning step after the at least one bond-strengthening annealing step, so that a transferred layer corresponding to a portion of the first wafer is formed.

11. The process according to claim 10 , wherein the second wafer is a sapphire substrate.

12. The process according to claim 11 , wherein the thinning step comprises grinding followed by etching of the first wafer.

13. The process according to claim 12 , wherein the grinding is conducted using a grinding wheel having a work surface which comprises abrasive particles with an average size larger than 6.7 microns.

14. The process according to claim 13 , wherein the contact force of the grinding wheel on the first wafer is no greater than 222.5 Newtons.

15. A process for forming a transferred layer corresponding to a portion of a first wafer in a heterostructure, comprising:

forming a heterostructure by bonding first and second wafers together wherein the second wafer has a thermal expansion coefficient that is higher than the thermal expansion coefficient of the first wafer;

trimming only an annular portion of an edge of the first wafer so that the edge is at least partially reduced in thickness; and

conducting at least one bond-strengthening annealing step on the heterostructure after the first trimming step;

wherein the trimming is conducted after the bonding but before a thinning step of the first wafer and remaining annular portion.

16. The process according to claim 15 , which further comprises:

a second trimming step;

a first bond-strengthening annealing step conducted before the thinning step; and

a second bond-strengthening annealing step;

wherein the second trimming step is conducted before the second annealing step.

17. The process according to claim 16 ; wherein the second bond-strengthening annealing step is carried out at a higher temperature than the first bond-strengthening annealing step.

18. The process according to claim 1 , wherein the at least one bond-strengthening annealing step is carried out at a temperature of about 150 to 200° C. for a time of about 1 to 3 hours.

Assignments (2)
CHANGE OF NAME Recorded Mar 4, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027800/0911 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2010
From: VAUFREDAZ, ALEXANDRE
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 025525/0974 →