Fabrication of substrates with a useful layer of monocrystalline semiconductor material
View Patent ↗Methods for fabricating a semiconductor substrate. In an embodiment, the technique includes providing an intermediate support, providing a nucleation layer, and providing at least one bonding layer between the intermediate support and the nucleation layer to improve the bonding energy therebetween, and to form an intermediate assembly. The method also includes providing at least one layer of a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited semiconductor material to form a final support assembly comprising the target substrate, the deposited semiconductor material, and the intermediate assembly, and processing the final support assembly to remove the intermediate assembly. The result is a semiconductor substrate that includes the at least one layer of semiconductor material on the target substrate.
1. A method for fabricating a semiconductor substrate, comprising:
providing an intermediate support;
providing a nucleation layer;
providing at least one bonding layer between the intermediate support and the nucleation layer to improve the bonding energy therebetween, and to form an intermediate assembly;
depositing at least one layer of a semiconductor material upon the nucleation layer;
bonding a target substrate to the deposited semiconductor material to form a support assembly comprising the target substrate, the deposited semiconductor material, and the intermediate assembly; and
processing the support assembly to remove the intermediate assembly to provide a semiconductor substrate comprising the at least one layer of semiconductor material on the target substrate.
2. The method of claim 1 , wherein the nucleation layer comprises a barrier layer against diffusion of atoms from the intermediate support at epitaxial growth temperatures, and wherein the semiconductor material layer is epitaxially deposited on the nucleation layer.
3. The method of claim 2 , which further comprises providing a second barrier layer between the nucleation layer and the intermediate support prior to epitaxially depositing the semiconductor material layer.
4. The method of claim 1 , wherein the intermediate support further comprises a barrier layer that is resistant to diffusing elements derived from dissociation of the intermediate support at epitaxial growth temperatures, and wherein the semiconductor material is epitaxially deposited on the nucleation layer.
5. The method of claim 4 , wherein the barrier layer is formed by a deposition technique.
6. The method of claim 4 , wherein the barrier layer is first applied to the intermediate support and then the nucleation layer is applied to the barrier layer.
7. The method of claim 6 , wherein a layer of adhesive is applied to at least one of a surface of the barrier layer or a surface of the nucleation layer to define a bonding layer.
8. The method of claim 1 , wherein the nucleation layer is formed by a deposition technique.
9. The method of claim 1 , wherein the intermediate assembly is removed by etching.
10. The method of claim 9 , wherein the intermediate assembly is etched with an acid solution.
11. The method of claim 1 , wherein the intermediate assembly is provided by:
implanting atomic species into at least a portion of a source substrate to define the nucleation layer, wherein a main concentration of implanted atomic species defines a detachment zone;
applying the at least one bonding layer to at least one of a surface of the nucleation layer or to at least a portion of a surface of the intermediate support;
attaching the source substrate implanted with the atomic species, the at least one bonding layer, and at least a portion of the intermediate support together to form a structure; and;
treating the structure to detach the intermediate assembly from the source substrate at the detachment zone.
12. The method of claim 11 , wherein the treating step comprises applying thermal or mechanical stress to detach the nucleation layer from the support substrate.
13. The method of claim 11 , which further comprises affixing the nucleation layer to the at least one bonding layer and to the intermediate support by molecular bonding.
14. The method of claim 1 , wherein the intermediate support is selected from the group consisting of silicon, gallium arsenide, zinc oxide, lithium gallium oxide and lithium aluminum oxide.
15. The method of claim 1 , wherein the nucleation layer comprises at least one of silicon carbide, gallium nitride, or sapphire.
16. The method of claim 1 , wherein the semiconductor material comprises at least one mono or poly-metallic nitride.
17. The method of claim 16 , wherein the semiconductor material layer comprises gallium nitride, and further wherein the nucleation layer is selected from the group consisting of silicon carbide, gallium nitride and sapphire.
18. The method of claim 1 , wherein the final support assembly further comprises a reflective coating.
19. The method of claim 1 , wherein the at least one bonding layer comprises at least one of silicon oxide or silicon nitride.
20. The method of claim 1 , wherein the target substrate comprises at least one of monocrystalline or polycrystalline silicon.
21. The method of claim 1 , wherein the final support is chemically treated to remove at least one of the intermediate support or the nucleation layer.
22. The method of claim 1 ,
wherein the material of the nucleation layer is suitable for accommodating the thermal expansion of the intermediate support and the thermal expansion of the deposited semiconductor layer.
23. The method of claim 22 , wherein the intermediate support comprises a material having thermal expansion coefficients that minimize stresses that arise during variations in temperature.
24. The method of claim 22 , wherein the nucleation layer is gallium nitride.
25. The method of claim 22 , wherein the nucleation layer comprises a material from the group consisting of sapphire, silicon carbide, zinc oxide, silicon, gallium nitride, neodymium gallate, and lithium gallate.
26. The method of claim 22 , wherein the intermediate support comprises a material from the group consisting of silicon carbide, aluminum nitride, silicon, and sapphire.
27. The method of claim 22 , wherein the nucleation layer and the intermediate support have substantially the same chemical composition.
28. The method of claim 22 , wherein the nucleation layer includes a crystal lattice parameter sufficient for the epitaxial growth of the working layer on the nucleation layer such that the semiconductor layer has a dislocation concentration less than about 10 7 /cm 2 .
29. The method of claim 22 , further comprising providing a source substrate including the nucleation layer and a weakened zone, and detaching the nucleation layer from the source substrate at the weakened zone to transfer it to the intermediate support.
30. The method of claim 29 , wherein the weakened zone comprises implanted atomic species at a depth that corresponds to the thickness of the source substrate.
31. The method of claim 29 , wherein the nucleation layer is detached from the source substrate by application of at least one of heat treatment, mechanical stress, chemical etching, or a combination thereof.
32. The method of claim 22 , which further comprises preparing the nucleation layer to receive the semiconductor layer, wherein the preparation includes at least one of polishing, annealing, smoothing, oxidation, and etching.
33. The method of claim 22 , further comprising removing the intermediate support such that it remains in a condition sufficient for recycling and reuse.