IP Library Granted Patent US 8,263,475
Granted Patent B2
US 8,263,475 · App. 12/747,099 · Granted Sep 11, 2012

Method for manufacturing heterostructures

Assignee: Soitec
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Quick Facts
Patent No.
US 8,263,475
App. No.
12/747,099
Granted
Sep 11, 2012
Kind
B2
Abstract

A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.

Claims (23)

1. A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics, which comprises:

providing donor and receiver substrates,

providing an oxide layer with a thickness of less than or equal to 25 nanometers on one of the donor substrate, the receiver substrate or on both substrates,

forming layer trapping through holes inside the oxide by heat treating the substrate(s) that contains the oxide layer for a sufficient time at a temperature between 900° C. and 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen,

bonding the substrates together at a bonding interface with the oxide layer(s) positioned between them,

reinforcing the bonding by annealing the substrates at a temperature between 25° C. and 500° C. such that the trapping holes retaining gas species at the bonding interface, and

transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.

2. The method of claim 1 , wherein the oxide layer comprises silicon oxide.

3. The method of claim 2 , wherein the silicon oxide layer is formed or deposited upon the substrate(s) at a thickness of less than or equal to 10 nanometers.

4. The method of claim 1 , wherein the heat treating for forming the trapping holes is carried out by rapid heat annealing for a duration comprised between about 30 seconds and 2 minutes.

5. The method of claim 1 , wherein the heat treating for forming the trapping holes is carried out in an epitaxy support for a duration of at least 10 minutes.

6. The method of claim 1 , wherein the trapping holes have a diameter of three micrometers at most.

7. The method of claim 1 , wherein at least one of the substrates comprises silicon.

8. The method of claim 1 , which further comprises etching the substrate(s) containing the silicon oxide layer facing the trapping holes after the heat treating in order to increase trapping hole depth.

9. The method of claim 7 , wherein the etching is conducted with hydrochloric acid.

10. The method of claim 1 , wherein the oxide layer is obtained by thermal oxidation of the substrate(s) or by chemical vapor deposition or low pressure chemical vapor deposition.

11. The method of claim 1 , wherein the oxide layer is a silicon oxide layer deposited by plasma under oxygen.

12. The method of claim 1 , wherein the transfer of the active layer comprises forming an embrittlement area inside the donor substrate prior to bonding the substrates together.

13. The method of claim 12 , wherein the silicon oxide layer is formed or deposited on the donor substrate and the embrittlement area is formed after the heat treating for forming the trapping holes.

14. The method of claim 1 , wherein the active layer has a thickness of between about 25 and 500 nanometers, and which further comprises heating the heterostructure in an inert or reducing atmosphere at a temperature of between about 1,100° C. and 1,300° C. for a time of between about a few minutes and a few hours to reduce the thickness of the oxide layer.

15. The method of claim 1 , which further comprises heating the heterostructure until the oxide layer is completely removed such that the active layer directly rests on the receiver substrate.

16. The method of claim 1 , wherein the active layer of the heterostructure comprises at least one oxide layer comprising holes for trapping gas species, with the oxide layer having a thickness of less than or equal to 50 nm, and with the trapping holes present in a density of between 0.1 and 100 holes per square centimeter of surface area of the oxide layer and each having a diameter of less than or equal to 3 micrometers.

17. The method of claim 16 , wherein the oxide layer of the heterostructure comprises silicon oxide.

Assignments (2)
CHANGE OF NAME Recorded Mar 4, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027800/0911 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2010
From: RADU, IONUT; KONONCHUK, OLEG; BOURDELLE, KONSTANTIN
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 024782/0198 →
Priority Claims (1)
FR 08 50534 · Jan 29, 2008 · national
Continuity (1)
Related Publication 20100264458A1 · Oct 21, 2010