IP Library Granted Patent US 8,389,412
Granted Patent B2
US 8,389,412 · App. 13/257,164 · Granted Mar 5, 2013

Finishing method for a silicon on insulator substrate

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Quick Facts
Patent No.
US 8,389,412
App. No.
13/257,164
Granted
Mar 5, 2013
Kind
B2
Abstract

The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Claims (22)

1. A finishing method for a silicon-on-insulator (SOI) substrate to reduce flaking formation, the method comprising an oxide layer buried between an active silicon layer and a support layer comprising silicon, which comprises applying the following steps in succession:

a first rapid thermal annealing (RTA) of the SOI substrate;

a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness;

a second RTA of the substrate; and

a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness;

wherein at least one of the first and second RTA steps is conducted in a non-oxidizing atmosphere at a temperature of between 900° C. and 1300° C. for a time of less than three minutes.

2. The method according to claim 1 , wherein the finishing does not include any additional sacrificial oxidation step after the second sacrificial oxidation step.

3. The method according to claim 1 , wherein the first removed oxide thickness is more than 150 nm, and the second removed oxide thickness is less than 150 nm.

4. The method according to claim 1 , wherein the first removed oxide thickness is more than 200 nm.

5. The method according to claim 1 , wherein the first removed oxide thickness is more than 300 nm.

6. The method according to claim 1 , wherein the second removed oxide thickness is less than 130 nm.

7. The method according to claim 1 , wherein the second removed oxide thickness is close to 120 nm.

8. The method according to claim 1 , wherein the first or second sacrificial oxidation steps or both comprise thermal oxidation conducted at a temperature of between 700° C. and 1100° C.

9. The method according to claim 1 , wherein the first or second sacrificial oxidation steps or both comprise de-oxidation with acid.

10. A finishing method for reducing flaking formation in a silicon-on-insulator (SOI) substrate comprising an oxide layer buried between an active silicon layer and a support layer comprising silicon, which method comprises:

applying the following steps in succession:

a first rapid thermal annealing (RTA) of the SOI substrate conducted in a non-oxidizing atmosphere at a temperature of between 900° C. and 1300° C. for a time of less than three minutes;

a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness of more than 300 nm;

a second RTA of the substrate conducted in a non-oxidizing atmosphere at a temperature of between 900° C. and 1300° C. for a time of less than three minutes; and

a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness of less than 130 nm.

11. The method according to claim 10 , wherein the first or second sacrificial oxidation steps or both comprise thermal oxidation conducted at a temperature of between 700° C. and 1100° C.

12. The method according to claim 10 , wherein the first or second sacrificial oxidation steps or both comprise de-oxidation with acid.

Assignments (2)
CHANGE OF NAME Recorded Mar 4, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027800/0911 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2012
From: SCHWARZENBACH, WALTER; KERDILES, SEBASTIEN; REYNAUD, PATRICK; ECARNOT, LUDOVIC; NEYRET, ERIC
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 027653/0759 →