IP Library Assignment 014646/0812
Patent Assignment
Reel/Frame 014646/0812

Assignment of Assignor's Interest

Recorded: 2003-11-07 Pages: 25
Assignors
BINAR GRAPHICS, INC.
Executed: 2003-10-09
DIAMOND MEDIA SYSTEMS, INC.
Executed: 2003-10-09
FRONT PATH, INC.
Executed: 2003-10-09
MICRONICS COMPUTERS, INC.
Executed: 2003-10-09
SONICBLUE INCORPORATED
Executed: 2003-10-09
Assignee
TREPTON RESEARCH GROUP
2700 MISSION COLLEGE BLVD., M/S 140Q, SANTA CLARA, CALIFORNIA, 95054
Covered Properties (67)
Memory Controller and Method Determining Empty/Full Status of a Fifo Memory Using Gray Code Counters
Patent: 5,426,756 →
Application: 07/928,552 →
Method of Resetting a Computer Video Display Mode
Patent: 5,420,605 →
Application: 08/023,945 →
Method of Resetting a Computer Video Display Mode
Patent: 5,477,241 →
Application: 08/124,386 →
Method of Resetting a Computer Video Display Mode
Patent: 5,648,795 →
Application: 08/315,586 →
Data Processing System and Apparatus with Prioritized Processing of First Graphic Event Data and Second Graphic Event Data
Patent: 5,784,043 →
Application: 08/401,454 →
Resource Allocation with Parameter Counter in Multiple Requester System
Patent: 5,623,634 →
Application: 08/448,003 →
Partitioned Decompression of Audio Data Using Audio Decoder Engine for Computationally Intensive Processing
Patent: 5,719,998 →
Application: 08/489,489 →
Shared Virtual Desktop Collaborative Application System
Patent: 6,204,847 →
Application: 08/503,453 →
Modular Virtualizing Device Driver Architecture
Patent: 6,393,495 →
Application: 08/561,349 →
Device Driver Architecture Supporting Emulation Environment
Patent: 6,009,476 →
Application: 08/561,354 →
Context Virtualizing Device Driver Architecture
Patent: 5,910,180 →
Application: 08/561,360 →
Dynamic Programmable Mode Switching Device Driver Architecture
Patent: 6,289,396 →
Application: 08/561,412 →
Mother Board with Flexible Layout for Accommodating Computer System Design Options
Patent: 5,703,760 →
Application: 08/568,661 →
Graphics Display System with a Low Level Hardware Dependent Graphics Library
Patent: 5,675,773 →
Application: 08/576,872 →
Circuit Board Mounting Brackets with Convective Air Flow Apertures
Patent: 5,684,674 →
Application: 08/584,321 →
Multiple Parallel Digital Data Stream Channel Controller
Patent: 6,044,225 →
Application: 08/596,921 →
Sigma-Delta Digital-to-Analog Conversion System and Process Through Reconstruction and Resampling
Patent: 5,748,126 →
Application: 08/612,691 →
Fan with Transition Chamber for Providing Enhanced Convective Flow
Patent: 5,586,865 →
Application: 08/613,247 →
Multiple Parallel Digital Data Stream Channel Controller Architecture
Patent: 5,822,553 →
Application: 08/614,729 →
Mixed Voltage, Multi-Rail, High Drive, Low Noise, Adjustable Slew Input/Output Buffer
Patent: 5,862,390 →
Application: 08/616,835 →
Low Latency Transport of Signals in an Error Correcting Data Modem
Patent: 5,946,347 →
Application: 08/655,834 →
Mother Board with Auxiliary Conductors in Parallel with Power Connectors
Patent: 5,777,276 →
Application: 08/686,552 →
Method of Operating a Portable Interactive Graphics Display Tablet and Communications Systems
Patent: 6,052,120 →
Application: 08/722,753 →
Computer System Supporting Portable Interactive Graphics Display Tablet and Communications Systems
Patent: 6,084,584 →
Application: 08/725,004 →
Liquid Crystal Cell Filling Method and Apparatus
Patent: 5,725,032 →
Application: 08/795,052 →
Voltage Tolerant Input/Output Buffer
Patent: 5,907,249 →
Application: 08/801,002 →
In-Line Control of Telephony Device
Patent: 6,011,836 →
Application: 08/805,081 →
Transformerless Data Access Arrangement
Patent: 5,875,235 →
Application: 08/813,343 →
Method of Resetting a Computer Video Display Mode
Patent: 5,767,834 →
Application: 08/820,950 →
Enhanced Scsi Transmitter and Adapter
Patent: 6,041,373 →
Application: 08/862,567 →
Method of Embedding Page Address Translation Entries Within a Sequentially Accessed Digital Audio Data Stream
Patent: 6,065,104 →
Application: 08/899,355 →
Voltage Tolerant Bus Hold Latch
Patent: 5,903,180 →
Application: 08/900,084 →
Coated Optical Fiber
Patent: 5,835,656 →
Application: 08/902,286 →
System and Method for a Mixed Voltage Drive System for Floating Substrate Technology
Patent: 5,966,036 →
Application: 08/926,174 →
Multiple-Port Ring Buffer
Patent: 5,896,322 →
Application: 08/956,710 →
Voltage Tolerant Buffer
Patent: 6,208,167 →
Application: 08/974,073 →
Processor Having Multiple Datapath Instances
Patent: 6,044,448 →
Application: 08/991,392 →
Output Buffer Circuit and Method That Compensate for Operating Conditions and Manufacturing Processes
Patent: 6,040,737 →
Application: 09/005,077 →
Fast Adder/Subtractor for Signed Floating Point Numbers
Patent: 6,175,851 →
Application: 09/020,152 →
Multiple Mode Analog Joystick Interface
Patent: 6,084,573 →
Application: 09/039,283 →
Modifying Circuit Designs Running from Both Edges of Clock to Run from Positive Designs Running from Both Edges of Clock to Run from Positive Edge
Patent: 6,370,662 →
Application: 09/039,973 →
Publication: US 2001/0052094
Voltage Level Shift System and Method
Patent: 6,005,432 →
Application: 09/053,555 →
Programmable Digital Signal Processing System Supporting Dynamically Redefinable Processing Functions
Patent: 6,134,605 →
Application: 09/060,745 →
Signal Processing System with Distributed Uniform Memory
Patent: 6,256,723 →
Application: 09/060,746 →
Method of Configuring a Functionslly Redefinable Signal Processing System
Patent: 6,088,785 →
Application: 09/060,747 →
Dsp Code Swapping with Continuous Dsp Execution
Patent: 6,205,522 →
Application: 09/060,936 →
Multiple Input Signature Testing & Diagnosis for Embedded Blocks in Integrated Circuits
Patent: 6,158,033 →
Application: 09/075,350 →
Tunable Digital Oscillator Circuit and Method for Producing Clock Signals of Different Frequencies
Patent: 6,075,398 →
Application: 09/088,645 →
Edge-Triggered Scan Flip-Flop and One-Pass Scan Synthesis Methodology
Patent: 6,389,566 →
Application: 09/088,754 →
Efficient Routing from Multiple Sources to Embedded Dram and Other Large Circuit Blocks
Patent: 6,169,418 →
Application: 09/103,757 →
Hybrid Circuit Model Simulator for Accurate Timing and Noise Analysis
Patent: 6,212,490 →
Application: 09/104,049 →
System and Method for Efficiently Transferring Information Between Processors
Patent: 6,112,262 →
Application: 09/128,220 →
Vertically Stackable Integrated Circuit
Patent: 6,093,029 →
Application: 09/149,549 →
Voltage Tolerant Input/Output Buffer
Patent: 5,973,511 →
Application: 09/225,650 →
Bracket for Mounting a Circuit Board Assembly on a Mother Board
Patent: 6,160,707 →
Application: 09/241,107 →
Multiple-Port Ring Buffer
Patent: 6,052,312 →
Application: 09/252,638 →
Differential Charge Pump with Low Voltage Common Mode Feedback Circuit
Patent: 6,275,097 →
Application: 09/285,320 →
Skew-Independent Memory Architecture
Patent: 6,393,600 →
Application: 09/320,191 →
Method for Ensuring Security of Program Data in One-Time Programmable Memory
Patent: 6,160,734 →
Application: 09/322,800 →
Single Rail Domino Logic for Four-Phase Clocking Scheme
Patent: 6,265,899 →
Application: 09/326,161 →
Read Data Valid Loop-Back for High Speed Synchronized Dram Controller
Patent: 6,519,688 →
Application: 09/676,460 →
System and method for efficiently implementing a double data rate memory architecture
Patent: 6,356,509 →
Application: 09/729,869 →
Shared Virtual Desktop Collaborative Application System
Patent: 6,859,928 →
Application: 09/753,983 →
Publication: US 2001/0004746
Browser System and Method
Patent: 8,171,158 →
Application: 09/818,415 →
Differential Charge Pump with Low Voltage Common Mode Feedback Circuit
Patent: 6,515,536 →
Application: 09/882,637 →
Publication: US 2001/0030572
Glitch free reset circuit
Application: 09/944,963 →
Server enclosure
Patent: 447,135 →
Application: 29/129,604 →
Related Assignments (9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest (Re-Record to Add Additional Pages to the Record on a Previously Recorded Document at Reel 7992, Frame 0645. Original Recording Consisted of 6 Pages. the Recording Should Have Been a Total of 7 Pages. May 24, 1996
From: GIFFORD, JAMES K.; BEGUR, SRIDHAR; LEWIS, ADRIAN; SPENCER, DONALD J.
To: DIAMOND MULTIMEDIA SYSTEMS, INC.
Reel/Frame 008111/0092 →
Assignment of Assignor's Interest Jul 26, 1996
From: ZHU, XIAO FENG
To: MICRONICS COMPUTERS INC.
Reel/Frame 008127/0460 →
Security Agreement Aug 29, 1996
From: CIRRUS LOGIC, INC.
To: BANK OF AMERICA NATIONAL TRUST & SAVINGS ASSOCIATION AS AGENT
Reel/Frame 008113/0001 →
Assignment of Assignor's Interest Nov 8, 1996
From: KU, CHARLENE S.; STEARNS, CHARLES C.; TAO, OLIVE T.
To: S3, INCORPORATED
Reel/Frame 008214/0666 →
Assignment of Assignor's Interest Apr 20, 2004
From: SONICBLUE INCORPORATED
To: TREPTON RESEARCH GROUP, INC.
Reel/Frame 014532/0711 →
Assignment of Assignor's Interest Apr 20, 2004
From: BINAR GRAPHICS, INC.
To: TREPTON RESEARCH GROUP, INC.
Reel/Frame 014532/0676 →
Assignment of Assignor's Interest Apr 20, 2004
From: MICRONICS COMPUTERS, INC.
To: TREPTON RESEARCH GROUP, INC.
Reel/Frame 014532/0688 →
Assignment of Assignor's Interest Apr 20, 2004
From: DIAMOND MULTIMEDIA SYSTEMS, INC.
To: TREPTON RESEARCH GROUP, INC.
Reel/Frame 014532/0694 →
Assignment of Assignor's Interest Apr 9, 2007
From: TREPTON RESEARCH GROUP
To: ALTERA CORPORATION
Reel/Frame 019140/0818 →