IP Library › Assignment 008113/0001
Patent Assignment
Reel/Frame 008113/0001

Security Agreement

Recorded: 1996-08-29 Pages: 108
Assignor
CIRRUS LOGIC, INC.
Executed: 1996-04-30
Assignee
BANK OF AMERICA NATIONAL TRUST & SAVINGS ASSOCIATION AS AGENT
1455 MARKET STREET, SAN FRANCISCO, CALIFORNIA, 94103
Covered Properties (299)
Reed-Solomon Code Encoder and Syndrome Generator Circuit
Patent: 4,777,635 →
Application: 06/895,034 →
Fast Remainder Decoding for a Reed-Solomon Code
Patent: 4,839,896 →
Application: 07/012,824 →
Shared Circuitry for the Encoding and Syndrome Generation Functions of a Reed-Solomon Code
Patent: 4,763,332 →
Application: 07/020,503 →
Vga Controller Circuitry
Application: 07/811,944 →
Process for Producing Shaded Images on Display Screens
Application: 07/813,036 →
Process for Producing Shaded Color Images on Display Screens
Application: 07/865,031 →
Vga Color System for Personal Computers
Patent: 5,574,478 →
Application: 07/874,038 →
Flexible Processor-Driven Control of Scsi Buses Utilizing Tags Appended to Data Bytes to Determine Scsi-Protocol Phases
Patent: 5,524,268 →
Application: 07/904,807 →
Flexible Disk Formats and Down Load of Formatter Control Storage
Application: 07/905,588 →
Bit Rate Doubler for Serial Data Transmission or Storage
Patent: 5,805,632 →
Application: 07/979,573 →
Register-Read Acknowledgment and Prioritization for Integration with a Hardware-Based Interrupt Acknowledgment Mechanism
Patent: 5,566,352 →
Application: 08/000,774 →
Heat Sealable Base Films
Patent: 5,302,442 →
Application: 08/009,161 →
Spectral Smoothing Filter
Application: 08/043,662 →
Reed-Solomon Code System Employing K-Bit Serial Techniques for Encoding and Burst Error Trapping
Patent: 5,659,557 →
Application: 08/056,839 →
Process for Producing Shaded Colored Images Using Dithering Techniques
Patent: 5,757,347 →
Application: 08/061,802 →
Dithering Process for Producing Shaded Images on Display Screens
Patent: 5,748,163 →
Application: 08/061,804 →
Burst Comparison and Sequential Technique for Determining Servo Control in a Mass Storage Disk Drive Device
Application: 08/071,472 →
Integrated Circuit Servo System Control for Computer Mass Storage Device Wit Distributed Control Functionality to Reduce Transport Delay
Application: 08/071,773 →
Method and Apparatus for Detecting the Connection Status of an Extension Phone Connected to a Voice/Fax/Data Modem
Application: 08/088,203 →
Method and System for Generating Dynamic Zoom Codes
Patent: 5,542,038 →
Application: 08/098,840 →
System and Method for the Mixing of Graphics and Video Signals
Application: 08/098,846 →
System and Method for Processing Multiple Received Signal Sources
Patent: 6,073,158 →
Application: 08/099,083 →
Voltage Reference and Current Source for Video Dac
Patent: 5,410,311 →
Application: 08/099,158 →
Dac Achieving Monotonicity with Equal Sources and Shift Array
Patent: 5,539,405 →
Application: 08/099,835 →
Charged Particle Beam Scattering System
Patent: 5,440,133 →
Application: 08/102,770 →
Managing Audio Data Using a Graphics Display Controller
Patent: 5,553,220 →
Application: 08/118,153 →
Method and Apparatus for Emulating a Telephone with a Modem and Headset
Patent: 5,533,105 →
Application: 08/121,615 →
Automatic Bus Setting, Sensing and Switching Interface Unit
Patent: 5,594,874 →
Application: 08/130,090 →
Image Rotation for Video Displays
Patent: 6,208,325 →
Application: 08/130,255 →
Dual Display Video Controller
Patent: 6,215,459 →
Application: 08/130,577 →
Vga Controller Circuitry
Patent: 5,581,279 →
Application: 08/147,456 →
Finite Field Inversion
Application: 08/147,758 →
Apparatus and Method for Programming the Setup, Command and Recovery Time Periods Within a Transaction Cycle
Application: 08/149,102 →
Napnop Circuit for Conserving Power in Computer Systems
Patent: 5,546,037 →
Application: 08/151,876 →
Rotation-Regulation Circuit, and Associated Method, for a Rotating Disk Drive System
Application: 08/167,778 →
Differential Amplifier and Variable Delay Stage for Use in a Voltage Controlled Oscillator
Application: 08/169,158 →
Method and Apparatus for Emulating Telephonic Communications with a Modem and Headset
Patent: 5,524,047 →
Application: 08/173,761 →
Video Font Cache
Patent: 5,539,428 →
Application: 08/176,563 →
Tagged Data Compression for Parallel Port Interface
Application: 08/178,673 →
Apparatus and Method for Interfacing a Peripheral Device Having a Rom Bios to a Pci Bus
Application: 08/178,942 →
Synchronous Read Channel Employing Discrete Time Timing Recovery Transition Detector, and Sequence Detector
Patent: 5,812,334 →
Application: 08/210,302 →
Filtering a Read Signal to Attenate Secondary Pulses Caused by Pole Tips of a Thin Film Magnetic Read Head
Patent: 5,623,377 →
Application: 08/222,666 →
Apparatus, Systems and Methods for Processing Video Data in Conjunction with a Multi-Format Frame Buffer
Patent: 5,506,604 →
Application: 08/223,845 →
Pcmcia Video Card
Patent: 5,642,139 →
Application: 08/235,761 →
Variable Pixel Depth and Format for Video Windows
Patent: 5,608,864 →
Application: 08/235,764 →
Method and Apparatus for Expanding and Centering Vga Text and Graphics
Patent: 5,521,614 →
Application: 08/235,827 →
Method and Apparatus for Calibrating a Prml Read Channel Integrated Circuit
Application: 08/236,719 →
Method and Apparatus for Dynamically Adjusting the Number of Stages of a Multiple Stage Pipeline
Application: 08/247,657 →
Method and Apparatus for Detecting and Decoding Data in a Prml Class-Iv Digital Communication Channel
Patent: 5,576,707 →
Application: 08/257,853 →
Method and Apparatus for Encoding Data in a Prml Class-Iv Digital Communication Channel
Patent: 5,544,178 →
Application: 08/258,308 →
Apparatus for Quantizing Pixel Information to an Output Video Display Space
Patent: 5,402,506 →
Application: 08/265,496 →
Video Window Generator with Scalable Video
Patent: 5,402,513 →
Application: 08/266,164 →
Method and Apparatus for Interfacing Between Peripherals of Multiple Formats and a Single System Bus
Patent: 5,727,184 →
Application: 08/266,975 →
Dual Bank Memory and Systems Using the Same
Patent: 5,506,810 →
Application: 08/291,093 →
Fast Recovering Charge Pump for Controlling a Vco in a Low Power Clocking Circuit
Patent: 5,523,724 →
Application: 08/293,676 →
Method and Apparatus for Correcting Errors in Pixel Characteristics When Interpolating Polygons into a Pixel Grid
Patent: 5,625,768 →
Application: 08/299,739 →
Crc/Edc Checker System
Patent: 5,592,498 →
Application: 08/306,917 →
Multipurpose Error Correction Calculation Circuit
Patent: 5,555,516 →
Application: 08/306,918 →
Versatile Error Correction System
Patent: 5,592,404 →
Application: 08/307,259 →
A Host Interface Circuit for Interfacing Peripheral Devices to Both Dma and Non-Dma Type Buses
Application: 08/307,965 →
Method and Apparatus for Providing Register Anfd Interrupt Compatibility Between Non-Identical Integrated Circuits
Application: 08/308,166 →
Method and Apparatus for Providing Register Compatibility Between Non-Identical Integrated Circuits
Patent: 5,796,981 →
Application: 08/308,167 →
Minimum Latency Asynchronous Data Path Controller in a Digital Recording System
Application: 08/308,179 →
Header Detect Method and Apparatus for an Optical Media Decoder
Application: 08/309,962 →
Method and Apparatus for Detecting the Transfer of a Wrong Sector
Application: 08/310,973 →
Timing Recovery for Synchronous Partial Response Recording
Application: 08/313,491 →
Fifo and Method of Operating Same Which Inhibits Putput Transitions When the Last Cell Is Read or When the Fifo Is Erased
Patent: 6,374,313 →
Application: 08/315,792 →
Method and Apparatus for Generating Hardware Icons and Cursors
Patent: 5,668,571 →
Application: 08/316,014 →
Programmable Audio-Video Synchronization Method and Apparatus for Multimedia Systems
Patent: 5,594,660 →
Application: 08/316,015 →
Flicker Reduction and Size Adjustment for Video Controller with Interlaced Video Output
Patent: 5,510,843 →
Application: 08/316,167 →
Cyclical Redundancy Check Method and Apparatus
Patent: 5,671,237 →
Application: 08/325,717 →
Detecting Servo Data and Servo Bursts from Discrete Time Samples of an Analog Read Signal in a Sampled Amplitude Read Channel
Patent: 5,668,678 →
Application: 08/325,842 →
Error Correction Method and Apparatus
Patent: 5,602,857 →
Application: 08/326,126 →
Method and Apparatus for Combining Controller Firmware Storage and Controller Logic in a Mass Storage System
Patent: 5,606,660 →
Application: 08/326,884 →
Error Correction Method and Apparatus for Disk Drive Emulator
Patent: 5,668,976 →
Application: 08/327,681 →
Method and Apparatus for Implementing a Dma Timeout Counter Feature
Patent: 5,826,107 →
Application: 08/329,360 →
Peripheral Interface Circuit Which Snoops Commands to Determine When to Perform Dma Protocol Translation
Patent: 5,655,145 →
Application: 08/329,554 →
Interface Circuit for Transferring Data Between Host Device and Mass Storage Device in Response to Designated Address in Host Memory Space Assigned as Data Port
Patent: 5,592,682 →
Application: 08/329,557 →
Read Channel Having Auto-Zeroing and Offset Compensation, and Power-Down Between Servo Fields
Patent: 5,648,738 →
Application: 08/333,488 →
Graphics Accelerator with Dual Memory Controllers
Patent: 5,664,162 →
Application: 08/333,628 →
Interpolation Rendering of Polygons into a Pixel Grid
Application: 08/333,841 →
Display List Processor for Operating in Processor and Coprocessor Modes
Patent: 5,706,478 →
Application: 08/338,341 →
Circuits, Systems, and Methods for Accounting for Defective Cells in a Memory Device
Application: 08/340,163 →
Channel Quality Circuit in a Sampled Amplitude Read Channel
Patent: 5,754,353 →
Application: 08/340,939 →
Equalization for Sample Value Estimation and Sequence Detection in a Sampled Amplitude Read Channel
Patent: 5,585,975 →
Application: 08/340,993 →
Real Time Media Defect Scanning in a Sampled Amplitude Read Channel
Patent: 5,563,746 →
Application: 08/341,234 →
Pid Loop Filter for Timing Recovery in a Sampled Amplitude Read Channel
Patent: 5,572,558 →
Application: 08/341,257 →
Decimation Dc Offset Control in a Sampled Amplitude Read Channel
Patent: 5,583,706 →
Application: 08/341,723 →
Method and Apparatus for Compensating Crosstalk in Liquid Crystal Displays
Application: 08/342,783 →
Network Controller Having Automatically Invoked Dma Data Transfer
Application: 08/343,073 →
Network Controller for Switching into Dma Mode Based on Anticipated Memory Overflow and Out of Dma Mode When the Host Processor Is Available
Application: 08/343,794 →
Circuits, Systems and Methods for Controlling the Display of Blocks of Data on a Display Screen
Application: 08/349,894 →
Multiprocessor System for Digital Signal Processing
Application: 08/352,900 →
Low-Power, High-Performance Barrel Shifter
Patent: 5,555,202 →
Application: 08/353,280 →
Stream Synchronization Method and Apparatus for Mpeg Playback System
Patent: 5,815,634 →
Application: 08/358,610 →
Method and Apparatus for Audio and Video Synchronizing in Mpeg Playback Systems
Patent: 5,598,352 →
Application: 08/358,611 →
Two Cycle Asynchronous Fifo Queue
Patent: 5,550,780 →
Application: 08/359,298 →
Memory Bandwidth Optimization
Patent: 5,611,041 →
Application: 08/359,315 →
Limiter Circuit Producing Data by Use of Comparison in Effective Digit Number of Data
Patent: 5,504,697 →
Application: 08/360,359 →
Pipelined Alignment Shifter and Method for Universal Bit Field Boundary Alignment
Application: 08/362,296 →
Arrangement and Method of Arbitration for a Resource with Shared User Request Signals and Dynamic Priority Assignment
Patent: 5,623,672 →
Application: 08/363,039 →
Apparatus for Controlling Fifo Buffer Data Transfer by Monitoring Bus Status and Fifo Buffer Thresholds
Patent: 5,771,356 →
Application: 08/368,562 →
Low Power Phase Lock Loop Clocking Circuit for Battery Powered Systems
Patent: 5,548,250 →
Application: 08/368,863 →
Low Power High Speed Cmos Current Switching Circuit
Patent: 5,548,238 →
Application: 08/369,002 →
Method and an Arrangement for Handshaking on a Bus to Transfer Information Between Devices in a Computer System
Patent: 5,564,114 →
Application: 08/369,968 →
Backward Compatibility for Plug and Play Systems
Patent: 5,634,075 →
Application: 08/371,304 →
Improved Memory Controller for Decoding a Compressed/Encoded Video Data Frame
Patent: 5,838,380 →
Application: 08/372,794 →
System and Method for Displaying Closed Caption Data on a Pc Monitor
Patent: 5,543,850 →
Application: 08/373,617 →
Apparatus, Systems and Methods for Controlling Graphics and Video Data in Multimedia Data Processing and Display Systems
Patent: 5,598,525 →
Application: 08/376,919 →
Booth Multiplier with High Speed Output Circuitry
Patent: 5,638,313 →
Application: 08/380,172 →
Booth Multiplier with Low Power, High Performance Input Circuitry
Patent: 5,734,601 →
Application: 08/380,174 →
Circuits, Systems and Methods for Improving Row Select Speed in a Row Select Memory Device
Patent: 5,701,143 →
Application: 08/381,189 →
Method and Apparatus for Automatically Maintaining a Predetermined Image Quality in a Display System
Patent: 6,121,949 →
Application: 08/382,355 →
An Adapter for Detecting Whether a Peripheral Is Standard or Multimedia Type Format and Selectively Switching the Peripheral to Couple or Bypass the System Bus
Patent: 5,630,174 →
Application: 08/383,582 →
Method and Apparatus for Interfacing Between Peripherals of Multiple Formats and a Single System Bus
Application: 08/386,818 →
Circuits, Systems and Methods for Testing Asic and Ram Memory Devices
Patent: 5,592,077 →
Application: 08/387,218 →
Computer System Host Adapter for Controlling Signal Levels to Peripheral Cards
Patent: 6,149,319 →
Application: 08/388,615 →
Sense Amplifier with Pull-Up Circuit for Accelerated Latching of Logic Level Output Data
Patent: 5,502,680 →
Application: 08/389,293 →
Low-Voltage Low-Power Dynamic Folded Sense Amplifier
Patent: 5,506,524 →
Application: 08/396,591 →
Defect Management for Automatic Track Processing Without Id Field
Application: 08/397,899 →
Defect Management for Automatic Track Processing Without Id Field
Application: 08/398,296 →
Memory Mapping Defect Management Technique for Automatic Track Processing Without Id Field
Patent: 5,848,438 →
Application: 08/399,095 →
Chatter Reduction in Sliding Mode Control of a Disk Drive Actuator
Application: 08/399,679 →
Sliding Mode Control of a Disk Drive Actuator
Application: 08/400,073 →
Servo Track Address Channel Code for D=1 Magnetic Recording
Application: 08/401,605 →
Video Processing Apparatus, Systems and Methods
Patent: 5,821,918 →
Application: 08/402,862 →
Video Processing Apparatus, Systems and Methods
Patent: 5,581,280 →
Application: 08/402,931 →
Video Processing Methods
Patent: 5,577,203 →
Application: 08/402,934 →
Video Processing Apparatus Systems and Methods
Patent: 5,625,379 →
Application: 08/402,935 →
Differential Amplifier and Variable Delay Stage for Use in a Voltage Controlled Oscillator
Patent: 5,600,280 →
Application: 08/404,133 →
Reset Based Computer Bus Identification Method and Circuit Resilient to Power Transience
Patent: 5,608,877 →
Application: 08/409,243 →
A Multi-Bit Data Storage Location
Patent: 5,567,963 →
Application: 08/410,868 →
Fabricating a Multi-Bit Storage Cell
Patent: 5,529,945 →
Application: 08/410,869 →
Method and Apparatus for Adaptive Dithering
Patent: 5,712,657 →
Application: 08/412,158 →
Error Correction Method and Apparatus for Headers
Patent: 5,600,662 →
Application: 08/412,277 →
Method and Apparatus for Monitoring a Row Address Strobe Signal in a Graphics Controller
Patent: 5,680,591 →
Application: 08/412,500 →
Method and Apparatus for Master Boot Record Shadowing
Patent: 5,701,477 →
Application: 08/413,234 →
Spacer Flash Cell Process
Patent: 5,640,031 →
Application: 08/413,349 →
Method and Appartus for Writing and Reading Entries in an Event Status Queue of a Host Memory
Patent: 5,774,745 →
Application: 08/414,467 →
Direct Memory Access for Storing and Retrieving Data Based on Packet Size
Patent: 5,797,033 →
Application: 08/414,468 →
Interrupt Request Control Logic Reducing the Number of Interrupts Required for I/O Data Transfer
Patent: 5,797,037 →
Application: 08/414,474 →
Servo Track Address Channel Code for PR4 Magnetic Recording
Patent: 5,737,142 →
Application: 08/414,690 →
System for Displaying Computer Generated Images on a Television Set
Patent: 5,896,179 →
Application: 08/414,996 →
Method and Arrangement for Clock Adjustment Using Programmable Period Binary Rate Multiplier
Patent: 5,588,145 →
Application: 08/415,021 →
A Low Order First Bit Serial Finite Field Multiplier
Patent: 5,680,340 →
Application: 08/415,475 →
Bus Driver/Receiver Circuitry and Systems and Methods Using the Same
Patent: 5,530,392 →
Application: 08/420,138 →
High Performance Method of and System for Selecting One of a Plurality of Ic Chips While Requiring Minimal Select Lines
Patent: 5,818,350 →
Application: 08/420,239 →
Semiconductor Memory Device for Mass Storage Block Access Applications
Application: 08/421,652 →
Semiconductor Memory Device for Block Access Applications
Patent: 5,523,979 →
Application: 08/421,653 →
Programmable Core-Voltage Solution for a Video Controller
Patent: 6,078,319 →
Application: 08/423,251 →
Continuous Page Random Access Memory and Systems and Methods Using the Same
Patent: 5,581,513 →
Application: 08/423,825 →
Circuits, Systems and Methods for Modifying Data Stored in a Memory Using Logic Operations
Patent: 5,732,024 →
Application: 08/424,653 →
Masterless Spindle Synchronization in a Multiple Disk Drive Storage System
Application: 08/432,449 →
Low-Voltage High-Performance Dual-Feedback Dynamic Sense Amplifier
Patent: 5,546,026 →
Application: 08/432,959 →
Latch-Type Current Sense Amplifier with Self-Regulating Inputs
Patent: 5,552,728 →
Application: 08/432,962 →
Defect Management for Automatic Track Processing Without Id Field
Patent: 6,560,055 →
Application: 08/434,457 →
High Performance Bus Driving/Receiving Circuits, Systems and Methods
Patent: 5,663,984 →
Application: 08/434,656 →
Sliding Mode Control of a Disk Drive Actuator for Positioning a Read/ Write Head Over a Selected Track During Seeking and Tracking Operations
Patent: 5,825,582 →
Application: 08/435,416 →
Chatter Reduction in Sliding Mode Control of a Disk Drive Actuator
Patent: 5,699,207 →
Application: 08/438,937 →
Animated Texture Map Apparatus and Method for 3-D Image Displays
Patent: 5,630,043 →
Application: 08/439,247 →
Fault Tolerant Sync Mark Detector Enabled Relative to a Frequency of an Acquisition Preamble for Sampled Amplitude Recording
Patent: 5,729,396 →
Application: 08/440,268 →
Sampled Amplitude Read Channel Employing Interpolated Timing Recovery
Patent: 5,696,639 →
Application: 08/440,508 →
Sampled Amplitude Read Channel Employing a User Data Frequency Synthesizer and a Servo Data Frequency Synthesizer
Patent: 5,796,535 →
Application: 08/440,515 →
Apparatus and Method for Producing Shaded Images on Display Screens
Patent: 5,751,265 →
Application: 08/442,836 →
Test Logic Circuit and Method for Verifying Internal Logic of an Integrated Circuit
Patent: 5,606,564 →
Application: 08/444,589 →
Technique and Apparatus for Color Expansion into a Non-Aligned 24 Bit Rgb Color-Space Format
Patent: 5,699,498 →
Application: 08/447,493 →
Interface Circuit for Transferring Data Between Host and Mass Storage by Assigning Address in the Host Memory Space and Placing the Address on the Bus
Patent: 5,603,052 →
Application: 08/451,877 →
High Performance Peripheral Interface
Application: 08/452,476 →
Method and Apparatus for Detecting the Connection Status of an Extension Phone Connected to a Voice/Fax Modem
Patent: 5,506,891 →
Application: 08/454,405 →
Voltage Controlled Oscillator Including Voltage Controlled Delay Circuit with Power Supply Noise Isolation
Patent: 5,559,476 →
Application: 08/455,311 →
Circuits System and Method for Transferring Data Between a Host Device and a Slave Device in a Single Cycle Using Alias Memory
Patent: 5,713,000 →
Application: 08/457,220 →
High Performance Peripheral Interface
Patent: 6,131,132 →
Application: 08/459,561 →
Method and Apparatus to Enable Docking/Undocking of a Powered- on Bus to a Docking Station
Application: 08/464,145 →
Target Peripheral Device Detection in a Multi-Bus System
Patent: 5,909,560 →
Application: 08/466,627 →
Extended Data Output Dram Interface
Patent: 5,546,344 →
Application: 08/466,629 →
Fast Synchronizing Digital Phase-Locked Loop for Recovering Clock Information from Encoded Data
Patent: 5,594,763 →
Application: 08/467,645 →
Error Correction Verification Method and Apparatus Using Crc Check Reminders
Patent: 5,629,949 →
Application: 08/468,108 →
Polarity Synchronization Method and Apparatus for Video Signals in a Computer System
Application: 08/471,129 →
Apparatus and Menthod for Providing Multiple Video Data Streams from a Single Source
Patent: 5,543,842 →
Application: 08/474,262 →
Brightness Control for Liquid Crystal Displays
Patent: 5,734,362 →
Application: 08/474,416 →
Apparatus, Systems and Methods for Generating Displays from Dual Source Composite Data Streams
Patent: 5,539,464 →
Application: 08/475,382 →
Clock Doubler Circuit with Duty Cycle Control
Application: 08/476,715 →
Apparatus and Method for Supporting Multiple Interrupt Protocols with Unequal Number of Interrupt Request Signals
Patent: 5,619,703 →
Application: 08/477,012 →
An Improved Method and Apparatus for Reading Ahead Dispplay Data into a Display Fifi Graphics Controller
Patent: 5,657,055 →
Application: 08/477,019 →
Method of Constructing a Plug and Play Compatible Bus Card Which Allows for Mass Production of the Bus Card
Application: 08/477,021 →
Defect Management and Split Field Processing in Disk Storage Systems
Patent: 5,740,358 →
Application: 08/478,354 →
Method and Apparatus for Identifying and Controlling a Target Peripheral Device in a Multiple Bus System
Patent: 5,673,400 →
Application: 08/478,579 →
Apparatus, Systems and Methods for Providing Multiple Video Data Streams from a Single Source
Patent: 5,539,465 →
Application: 08/478,937 →
Auto Latency Correction Method and Apparatus for Mpeg Playback System
Patent: 5,596,420 →
Application: 08/483,580 →
Pci Bus Master Retry Fixup
Patent: 6,104,876 →
Application: 08/483,583 →
Dual Displays Having Independent Resolutions and Refresh Rates
Patent: 5,841,418 →
Application: 08/483,584 →
Combinational Logic Circuit Eliminating Both Positive and Negative Glitches
Application: 08/486,555 →
Optimum Implementation of X-Y Clipping on Pixel Boundary
Patent: 5,668,941 →
Application: 08/493,665 →
Circuits, Systems and Methods for Testing Integrated Circuit Devices Including Logic and Memory Circuitry
Patent: 5,535,165 →
Application: 08/497,267 →
Transparent Bridge Between Buses of a Computer System and a Method of Interfacing the Buses to Operate as a Single Logical Bus
Patent: 5,734,850 →
Application: 08/498,240 →
Method and Apparatus for Flash Burst Error Correction
Patent: 5,727,003 →
Application: 08/498,275 →
Apparatus and Method for Reading Back Socket Power Status Information
Patent: 5,758,171 →
Application: 08/498,330 →
Sliding Mode Control of a Magnetoresistive Read Head for Magnetic Recording
Patent: 5,781,365 →
Application: 08/502,410 →
Pipeland Address Memories, and Systems and Methods Using the Same
Patent: 5,598,374 →
Application: 08/502,479 →
Chatter Reduction in Sliding Mode Control of a Disk Drive Actuator
Application: 08/507,621 →
An Apparatus and Method for Horizontally and Vertically Positioning a Vga Display Image on the Screen of a Flat Panel Display
Patent: 5,682,170 →
Application: 08/509,651 →
Direct Logical Block Addressing Flash Memory Mass Storage Architecture
Patent: 5,845,313 →
Application: 08/509,706 →
Unified System/Frame Buffer Memories and Systems and Methods Using the Same
Application: 08/512,574 →
Method and Apparatus for Acquiring Bus Transaction Data with No More Than Zero-Hold-Time
Patent: 5,623,645 →
Application: 08/513,374 →
Method and Apparatus for Acquiring Bus Transaction Address and Command Information with No More Than Zero-Hold-Time and with Fast Device Acknowledgement
Patent: 5,649,175 →
Application: 08/513,375 →
Fifo Based Receive Packet Throttle for Receiving Long Strings of Short Data Packets
Patent: 5,732,286 →
Application: 08/513,463 →
64 Bit Wide Video Front Cache
Patent: 5,742,298 →
Application: 08/514,887 →
A Non-Volatile Memory System of Multi-Level Transistor Cells and Methods Using Same
Patent: 5,596,526 →
Application: 08/515,188 →
Circuits and Methods for Controlling Frame Buffer Refresh
Application: 08/519,992 →
A Timing Gradient Smoothing Circuit in a Synchronous Read Channel
Patent: 5,576,904 →
Application: 08/520,520 →
Timing Recovery Frequency Error Detector for Sampled Amplitude Magnetic Recording
Patent: 5,642,243 →
Application: 08/521,145 →
Low Pin Count-Wide Memory Devices and Systems and Methods Using the Same
Patent: 5,537,353 →
Application: 08/521,867 →
Circuits, Systems and Methods for Controlling Substrate Bias in Integrated Circuits
Patent: 5,612,644 →
Application: 08/521,891 →
Method of and Architecture for Controlling System Data with Automatic Wear Leveling in a Semiconductor Non-Volatile Mass Storage Memory
Patent: 5,835,935 →
Application: 08/527,484 →
Memory Architecture and Devices, Systems and Methods Utilizing the Same
Patent: 5,568,431 →
Application: 08/531,755 →
Non-Glitch Clock Switching Circuit
Patent: 5,652,536 →
Application: 08/533,317 →
Fault Tolerant Sync Mark Detector for Camparing a Sign and Magnitude of a Detected Sequence to a Target Sync Mark in Sampled Amplitude Magnetic Recording
Patent: 5,793,548 →
Application: 08/533,797 →
Circuits, Systems and Methods for Memory Mapping and Display Control Systems Using the Same
Patent: 6,025,840 →
Application: 08/534,279 →
High Frequency Differential Vco with Common Biased Clipper
Patent: 5,568,099 →
Application: 08/534,538 →
Switching Circuit for Automatically Routing Audio and Data Signals Between a Modem and Variuous Devices According to a Selected Mode of Operation
Application: 08/536,025 →
Method and Apparatus for Dynamic Control of Clocks in a Multiple Clock Processor, Particularly for a Data Cache
Application: 08/536,223 →
Method and Apparatus for Upscaling Video Images in a Graphics Controller Chip
Application: 08/536,315 →
Method and Apparatus for Minimizing Number of Pixel Data Fetches Required for a Stretch Operation of Video Images
Patent: 5,727,139 →
Application: 08/536,553 →
Method and Apparatus for Overcoming a Slope Overload Condition While Using Differential Pulse Code Modulation Scheme
Patent: 5,768,507 →
Application: 08/536,577 →
Transaction Queue in a Graphics Controller Chip
Patent: 5,748,920 →
Application: 08/536,689 →
Dma Controller Arrangement Having Plurality of Dma Controllers and Buf Fer Pool Having Plurality of Buffers Accessible to Each of the Channel S of the Controllers
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Dma Controller Having Multiple Channels and Buffer Pool Having Plurali Ty of Buffers Accessible to Each Channel for Buffering Data Transferre D to and from Host Computer
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Memory Devices with Selectable Access Type and Methods Using the Same
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Circuits Systems and Methods for Reducing Power Loss During Transfer of Data Across a Conductive Line
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Table Driven Method and Apparatus for Automatic Split Field Processing
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High Performance Peripheral Interface with Read-Ahead Capability
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Method and Apparatus for Determining Representative Chrominance Components
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Single Chip Controller-Memory Device and a Memory Architecture and Methods Suitable for Implementing the Same
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Circuits, Systems and Methods for Interfacing Processing Circuitry with a Memory
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A Dual Bank Memory System with Output Multiplexing and Methods Using the Same
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Method and Apparatus for Reducing Flicker in Shaded Displays
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Memory Architecture Using Content Addressable Memory, and Systems and Methods Using the Same
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Method and Apparatus for Minimizing Effects of Slope Overload Condition When Using Differential Pulse Code Modulation Scheme
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Computer System with Multiple Pc Card Controllers and a Method of Controlling I/O Transfers in the System
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Method and Apparatus for Minimizing System Oscillations Caused by Acoustical Coupling
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Method and Apparatus for Upscaling Video Images When Pixel Data Used for Upscaling a Source Video Image Are Unavailable
Patent: 5,703,618 →
Application: 08/561,907 →
Multi-Bank Memory System and Method Having Addresses Switched Between the Row and Column Decoders in Different Banks
Patent: 5,761,694 →
Application: 08/565,388 →
System and Method for Using a Half-Clock Module to Implement Computer Timing Control Circuitry
Patent: 5,668,982 →
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Programmable Redundancy/Syndrome Generator
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Magnetic Disk Sampled Amplitude Read Channel Employing Interpolated Timing Recovery for Synchronous Detection of Embedded Servo Data
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Fixed Sample Rate Sampled Amplitude Read Channel for Zoned Magnetic Recording
Patent: 5,812,336 →
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Method and Apparatus for Converting Monochrome Pixel Data to Color Pixel Data
Patent: 5,854,620 →
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Method and Apparatus for Prefetching a Next Instruction Using Display List Processing in a Graphics Processor
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Application: 08/574,835 →
Method and Apparatus for Dynamic Object Identification After Z-Collision
Patent: 5,812,138 →
Application: 08/574,889 →
On-The-Fly Error Correction Using Thermal Asperity Erasure Pointers from a Sampled Amplitude Read Channel in a Magnetic Disk Drive
Patent: 5,701,314 →
Application: 08/576,742 →
System for Managing Direct Memory Access Transfer in a Multi-Channel System Using Circular Descriptor Queue, Descriptor Fifo, and Receive Status Queue
Patent: 5,870,627 →
Application: 08/576,868 →
Method and Apparatus for Placing Multiple Frames of Data in a Buffer in a Direct Memory Access Transfer
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Application: 08/576,869 →
Controller for Processing Different Pixel Data Types Stored in the Same Display Memory by Use of Tag Bits
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Application: 08/576,870 →
Tiled Memory Addressing with Programmable Tile Dimensions
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Graphics Display System with a Low Level Hardware Dependent Graphics Library
Patent: 5,675,773 →
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Video Port Interface Supporting Multiple Data Formats
Patent: 5,850,266 →
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Method and System for Reducing Numberic Counting Levels in Resampling Control Circuitry
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Application: 08/576,943 →
Dynamic Arbitration Priority
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Sdram Dimm Presence Detect Interface
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Sdram Memory Controller with Multiple Arbitration Points During a Memory Cycle
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Application: 08/577,584 →
System and Method for Multi-Level Gain Control
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Application: 08/577,652 →
Method and Apparatus for Optimizing Pixel Data Write Operations to a Tile Based Frame Buffer
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System and Method for Extracting Caption/Teletext Information from a Video Signal
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Application: 08/578,300 →
Automatic Step Generator for Self-Correction of Sampling
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Sdram Memory Controller While in Burst Four Mode Supporting Single Data Accesses
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Software Teletext Decoder Architecture
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System and Method for Providing a Precise Current Cell for Use with D/a Convertors
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Selective Low Power Clocking Apparatus and Method
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Communication Interface Unit Employing Two Multiplexer Circuits and Control Logic for Performing Parallel-to-Serial Data Conversion of a Selected Asynchronous Protocol
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Flexible Processor-Driven Scsi Controller with Buffer Memory and Local Processor Memory Coupled via Separate Buses
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Circuits Systems and Methods for Reducing Power Loss During Transfer of Data Across an I/O Bus
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Single Chip Controller-Memory Device with Interbank Cell Replacement Capability and a Memory Architecture and Methods Suitable for Implementing the Same
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System and Method for Detecting the Dram Architecture in a Computer
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Hardware Assist for Yuv Data Format Conversion to Software Mpeg Decoder
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System and Method Synchronizing Audio and Video Digital Data Signals During Playback
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Universal Mpeg Decoder with Scalable Picture Size
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Method and Arrangement for Shutting Off a Receive Channel in a Data Communications System
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Method and Apparatus for Handling Proprietary and Non-Proprietary Formatted Compact Discs in the Same Video Playblack System
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Method and Apparatus for Automatically Maintaining a Predetermined Image Quality in a Display System
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An Optical Disc Drive Comprising Switching Gains for Forcing Phase States to Follow a Sliding Line Trajectory in a Servo System
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System for Coupling Asynchronous Data Path to Field Check Circuit of Synchronous Data Path When the Asynchronous Data Path Communicating Data in Synchronous Format
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Wired Combinational Logic Circuit with Pullup and Pulldown Devices
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A Network Controller Using Held Data Frame Monitor and Decision Logic for Automatically Engaging Dma Data Transfer When Buffer Overflow Is Anticipated
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Method and Apparatus for Encoding History of File Access to Support Automatic File Caching on Portable and Desktop Computers
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Related Assignments (5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Sep 10, 2001
From: CIRRUS LOGIC, INC.
To: INTEL CORPORATION
Reel/Frame 012134/0685 →
Assignment of Assignor's Interest Nov 10, 2003
From: CIRRUS LOGIC, INC.
To: NVIDIA INTERNATIONAL, INC.
Reel/Frame 014646/0167 →
Change of Name Sep 15, 2007
From: S3 INCORPORATED
To: SONICBLUE INCORPORATED
Reel/Frame 019825/0493 →
Deed of Discharge Nov 26, 2012
From: BANK OF AMERICA NATIONAL TRUST & SAVINGS ASSOCIATION
To: CIRRUS LOGIC, INC.
Reel/Frame 029353/0747 →
Assignment of Assignor's Interest Dec 6, 2012
From: NVIDIA INTERNATIONAL INC.
To: NVIDIA CORPORATION
Reel/Frame 029418/0249 →