IP Library Assignment 014668/0347
Patent Assignment
Reel/Frame 014668/0347

Assignment of Assignor's Interest

Recorded: 2004-05-25 Pages: 3
Assignors
TSAO, CHUNG-WEN
Executed: 2004-05-14
TENG, CHIN-CHI
Executed: 2004-05-14
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property (1)
Two-Stage Clock Tree Synthesis with Buffer Distribution Balancing
Patent: 7,051,310 →
Application: 10/434,919 →
Publication: US 2004/0225984