Patent Assignment
Reel/Frame 014775/0168
Assignment of Assignor's Interest
Recorded: 2003-08-11
Pages: 8
Assignors
LIEN CHUEN-DER
Executed: 2003-08-04
AU, MARIO
Executed: 2003-08-05
DUH, JIANN-JENG
Executed: 2003-08-05
Assignee
INTEGRATED DEVICE TECHNOLOGY, INC.
2975 STENDER WAY, SANTA CLARA, CALIFORNIA, 95054
Covered Property
(1)
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same
Application:
10/639,163 →
Publication:
US 2004/0047209