IP Library Patent Application 10639163
Patent Application Utility
App. No. 10/639,163 · Confirmation No. 7751

FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same

Abandoned -- Failure to Respond to an Office Action View Publication ↗
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2006-10-13 ABN Abandonment 2 View
2006-06-01 EBCC.AD Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update 1 View
2006-05-30 EBCC.AD Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update 1 View
2006-02-22 CTNF Non-Final Rejection 7 View
2006-02-22 1449 List of References cited by applicant and considered by examiner 1 View
2006-02-22 892 List of references cited by examiner 1 View
2006-02-22 SRFW Search information including classification, databases and other search related notes 1 View
2006-02-22 FWCLM Index of Claims 1 View
2006-02-15 SRNT Examiner's search strategy and results 2 View
2004-03-05 IDS Information Disclosure Statement (IDS) Form (SB08) 3 View
2004-01-23 PETDEC Petition Decision 1 View
2003-11-24 PET. Petition Entered 10 View
2003-08-11 TRNA Transmittal of New Application 3 View
2003-08-11 A.PE Preliminary Amendment 1 View
2003-08-11 ABST Abstract 1 View
2003-08-11 CLM Claims 16 View
2003-08-11 CLM Claims 6 View
2003-08-11 DRW Drawings-only black and white line drawings 28 View
2003-08-11 OATH Oath or Declaration filed 4 View
2003-08-11 SPEC Specification 49 View
2003-08-11 WFEE Fee Worksheet (SB06) 1 View
2003-08-11 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
App. No.
10/639,163
Filed
2003-08-11
Pub. No.
US20040047209A1
Art Unit
2188