Patent Assignment
Reel/Frame 015299/0316
Assignment of Assignor's Interest
Recorded: 2004-05-05
Pages: 3
Assignors
LEE, LURNG-SHEHNG
Executed: 2004-03-10
TZENG, PEI-JER
Executed: 2004-03-10
KUO, CHIN-SHENG
Executed: 2004-03-10
HWU, JENN-GWO
Executed: 2004-03-10
Assignee
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
NO. 195, SEC. 4, CHUNG-HSING RD., CHU-TUNG, HSINCHU, R.O.C., TAIWAN
Covered Property
(1)
Process of Forming High-K Gate Dielectric Layer for Metal Oxide Semiconductor Transistor
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.
Corrective Assignment to Correct the Name of the Third Inventor (Chih-Sheng Kuo) on the Assignment Previously Recorded on Reel 015299 Frame 0316. Assignor(S) Hereby Confirms the Correct Name of the Third Inventor Should Be Chih-Sheng Kuo.
Jan 19, 2011
From: LEE, LURNG-SHEHNG; TZENG, PEI-JER; KUO, CHIH-SHENG; HWU, JENN-GWO
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 025663/0568 →
Assignment of Assignor's Interest
Feb 13, 2011
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: TRANSPACIFIC IP II LTD.
Reel/Frame 025799/0953 →